• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.7
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• pp.601-604
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• 2006

In this paper, we propose the single poly-Si Flash EEPROM device with a new structure which does not need the high voltage switching circuits. The device was designed, fabricated and characterized. From the measurement results, it was found that the program, the erase and the read operations worked properly. The threshold voltage was 3.1 V after the program in which the control gate and the drain were biased with 12 V and 7 V for $100{\mu}S$, respectively. And it was 0.4 V after the erase in which the control gate was grounded and the drain were biased with 11 V for $200{\mu}S$. On the other hand, it was found that the program and the erase speeds were significantly dependent on the capacitive coupling ratio between the control gate and the floating gate. The larger the capacitive coupling ratio, the higher the speeds, but the target the area per cell. The optimum structure of the cell should be chosen with the consideration of the trade-offs.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.17 no.2
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• pp.109-117
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• 2018

The experimental results are presented of an autonomous flight algorithm of a foldable quadcopter with airdrop launching functions. A foldable wing structure enabled the quadcopter to be inserted into a rocket container with limited space. The foldable quadcopter was then separated from the rocket in the air. The flight pattern was tracked using a global positioning system (GPS) with various sensors, including an inertial measurement unit (IMU) module until a designated target position was reached. Extensive field tests were conducted through an international rocket competition, ARLISS 2017, which was held in Black Rock Desert, Nevada, USA. The flight trajectory record of the experiments is stored in electrically erasable programmable read-only memory (EEPROM) embedded in the main control unit. The flight record confirmed that the quadcopter successfully separated from the rocket, executed flight toward the target for a certain length of time, and stably landed on the ground.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.351-354
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• 2008

실시간 요건을 필요로 하는 임베디드 시스템의 경우 예측가능성(predictability)이 매우 중요하다. 그렇기 때문에 이러한 시스템들은 가상 메모리를 사용하지 않는 단순한 실시간 운영체제(RTOS) 를 사용하는 경우가 일반적이다. 하지만, 임베디드 시스템에 요구되는 기능 요건들이 복잡해짐에 따라 Linux와 같은 가상 메모리 기반의 범용 운영체제를 채택하는 경우가 늘고 있으며, 이런 경향은 앞으로 더욱 심해질 전망이다. 가상메모리 시스템은 필요한 메모리 사용량을 줄일 수 있을 뿐만 아니라 응용 프로그램 개발과 디버깅을 용이하게 하기 때문에 기존의 복잡하고 어려운 실시간 운영체제의 개발환경을 사용하는 경우에 비해 높은 개발 생산성을 기대할 수 있다. 하지만, 가상 메모리 시스템의 요구 페이징 기법은 시스템의 예측가능성을 떨어뜨리기 때문에 일반적으로 실시간 요건을 필요로 하는 시스템에 적용되지 못하고 있다. 본 논문은 요구 페이징 기법의 사용을 전제로 한 임베디드 시스템의 실시간 요건을 만족시키기 위한 페이지 교체 기법을 제안한다.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.515-520
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• 2009

This paper presents the software design of RFID Educational system based on using 900MHz air interface between the reader and the tag. Software of the reader and active tag is developed on embedded environment and the software of PC controlling the reader is on window OS. ATmega128 processor is used for H/W of the reader and active tag, and C language is used for their developing. Programming on window OS used MFC. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Software design of 900MHz RFID educational system is done on the basis of these functions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1082-1091
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• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• Proceedings of the KSRS Conference
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• v.1
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• pp.417-420
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• 2006

In these days, mobile application dealing with information contents on mobile or handheld devices such as mobile communicator, PDA or WAP device face the most important industrial needs. The motivation of this study is the design and implementation of mobile application using high resolution satellite imagery, large-sized image data set. Although major advantages of mobile devices are portability and mobility to users, limited system resources such as small-sized memory, slow CPU, low power and small screen size are the main obstacles to developers who should handle a large volume of geo-based 3D model. Related to this, the previous works have been concentrated on GIS-based location awareness services on mobile; however, the mobile 3D terrain model, which aims at this study, with the source data of DEM (Digital Elevation Model) and high resolution satellite imagery is not considered yet, in the other mobile systems. The main functions of 3D graphic processing or pixel pipeline in this prototype are implemented with OpenGL|ES (Embedded System) standard API (Application Programming Interface) released by Khronos group. In the developing stage, experiments to investigate optimal operation environment and good performance are carried out: TIN-based vertex generation with regular elevation data, image tiling, and image-vertex texturing, text processing of Unicode type and ASCII type.

• Journal of IKEEE
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• v.12 no.2
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• pp.118-123
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• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.5
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• pp.229-235
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• 2018

As of in the year of 2016, 40 million ARM processors are being shipped everyday and more than 86 billion ARM processors are mounted in mobile communications, consumer electronics, enterprises, and embedded systems. Nationally, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Generally, highly expensive software programs are necessary for designing processors which makes it difficult to set up proper environments. However, ModelSim simulator provided by Altera is free and everybody can use it. In this paper, the VHDL language which is widely used in Europe, universities, and research centers around the world for the ASIC design is selected for designing 32-bit ARM processor and simulated by ModelSim. As a result, 37 instructions of ARMv4 has been successfully executed.