• Journal of IKEEE
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• 제16권3호
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Journal of the Korean Society for Precision Engineering
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• 제22권12호
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• pp.70-76
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• 2005

It is known that natural awakening of us in the morning is due to stimulation of the reticular activation system through biological clock in the suprachiasmatic nucleus of hypothalamus by the morning sunlight. If we sleep at dark rooms without windows and so without morning sunlight, thus, it is not easy fur us to get up refreshingly in the morning. In this paper, we propose an automatic sunrise household lighting system that helps us fer getting up cheerfully in the morning even if we sleep in dark rooms without morning sunlight. The proposed lighting system is an embedded system that turns automatically on the electric lamp and makes it brighter and brighter coincidently with the actual sunrise. The proposed system is composed of a PIC microcontroller with flash memory, a real-time clock IC, a D/A converter, an amplifier, a dimmer unit, a light bulb, a display panel and a keyboard. The validity of the proposed intelligent lighting system is demonstrated via a prototype production and experimentation.

• The Journal of Information Technology
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• 제6권3호
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• pp.65-73
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• 2003

The evaluation AP embedded Linux board is implemented. The board is made of IBM 405 GP processor, PPCBoot-1.2.1 boot loader, Linux-2.4.21 kernel and root file system. The evaluation board has two flash memories, boot flash and application flash of size 512Kbyte and 16Mbyte, respectively. And it supports IEEE 802.11a which provide the maximum throughput of 54Mbps in the 5.2GHz frequency band. MTD(Memory Technology Device) and JFFS2(Journalling Flash File System version 2) technologies are adopted to optimally package the system software, boot loader, kernel and root file system. And in order to optimize root file system, busybox package and tiny login are used. Linux kernel and root file system is combined together with mkimage utility.

• Journal of the Korean Institute of Intelligent Systems
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• 제14권4호
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• pp.424-430
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• 2004

This paper explains the construction of the filesystems which could be utilized in embedded systems as an implementation of ubiquitous computing. It includes the formal architecture of filesystem hierarchy for the DOC (Disk-On-Chip) filesystem and the flash filesystem based on the MTD (Memory Technology Devices). For DOC, the root filesystem and the user filesystem are constructed by the TrueFFS supported by the M-Systems. For MTD filesystem, the root filesystem is implemented in the fast RAM disk, and the user filesystem is implemented in the JFFS2 that supports large capacity. In order to support the GUI filesystem, the porting process of Qt/E is also included in this paper.

• IEMEK Journal of Embedded Systems and Applications
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• 제12권3호
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• pp.139-147
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• 2017

In recent years, non-volatile memory express (NVMe), a new host controller interface standard, has been adapted to overcome performance bottlenecks caused by the acceleration of solid state drives (SSD). Recently, performance breakthrough cases over AHCI based SATA SSDs by adapting NVMe based PCI Express (PCIe) SSD to servers and PCs have been reported. Furthermore, replacing legacy eMMC-flash storage with NVMe based storage is also considered for next generation of mobile devices such as smartphones. The Linux kernel includes drivers for NVMe support, and as the kernel version increases, the implementation of the NVMe driver code has changed. However, mobile devices are often equipped with older versions of Android operating systems (OSes), where the newest features of NVMe drivers are not available. Therefore, different features of different NVMe driver implementations are not well evaluated on Android OSes. In this paper, we analyze the response time of the NVMe driver for various Linux kernel version.

• IEMEK Journal of Embedded Systems and Applications
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• 제13권5호
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• pp.225-234
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• 2018

Control flow errors are caused by the vulnerability of memory and result in system failure. Signature-based control flow monitoring is a representative method for alleviating the problem. The method commonly consists of two routines; one routine is signature update and the other is signature verification. However, in the existing signature-based control flow monitoring, monitoring target application is tightly combined with the monitoring code, and the operation of monitoring in a single thread is the basic model. This makes the signature-based monitoring method difficult to expect performance improvement that can be taken in multi-thread and multi-core environments. In this paper, we propose a new signature-based control flow monitoring model that separates signature update and signature verification in thread level. The signature update is combined with application thread and signature verification runs on a separate monitor thread. In the proposed model, the application thread and the monitor thread are separated from each other, so that we can expect a performance improvement that can be taken in a multi-core and multi-thread environment.

• Convergence Security Journal
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• 제6권2호
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• pp.43-51
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• 2006

The existing electronic transaction protocol uses a cryptography algorithm that is not suitable for mobile environment because of limited memory and process ability. In this paper, we propose an efficient transaction protocol suitable for mobile embedded system. The proposed protocol reduces computation and process time by using ID-based cryptography algorithm and ECC (elliptic curve cryptosystem). It uses vendor authentication only in the first transaction, and from the second transaction, it requires transaction after authentication with session created by applying ECC technique. Therefore, the creation number of authentication for the vendor can be reduced from n to one. And it reduces process time because it provides the same security with 160 bits as with 1024 bits of RSA.

• ETRI Journal
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• 제30권4호
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• pp.576-586
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• 2008

In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.

• IEMEK Journal of Embedded Systems and Applications
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• 제12권1호
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• pp.1-10
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• 2017

Recently, with the ever-increasing complexity of industrial robot systems, it has been greatly attention to adopt a multi-core based motion controller with high cost-performance ratio. In this paper, we propose a software architecture that aims to utilize the computing power of multi-core processors. The key concept of our architecture is to use shared memory for the interplay between threads running on separate processor cores. And then, we have integrated our proposed architecture with an industrial standard compliant IDE for automatic code generation of motion runtime. For the performance evaluation, we constructed a test-bed consisting of a motion controller with Preempt-RT Linux based dual-core industrial PC and a 3-axis industrial robot platform. The experimental results show that the actuation time difference between axes is 10 ns in average and bounded up to 689 ns under $1000{\mu}s$ control period, which can come up with real-time performance for industrial robot.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권5B호
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• pp.526-531
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• 2009

In this paper, we propose new novel technique (ILCT: Instruction-Level Correlation Technique) which can detect tempered instructions by software attacks or hardware attacks before their execution. In conventional works, due to both high complex computation of cipher process and low processing speed of cipher modules, existing secure processor architecture applying cipher technique can cause serious performance degradation. While, the secure processor architecture applying ILCT with FEC does not incur excessive performance decrease by complexity of computation and speed of tampering detection modules. According to experimental results, total memory overhead including parity are increased in average of 26.62%. Also, secure programs incur CPI degradation in average of $1.20%{\sim}1.97%$.