• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.22-34
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• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Speech Sciences
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• v.11 no.2
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• pp.181-192
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• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.5
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• pp.576-580
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• 2010

Generally, due to the strong coherence between embedded software and hardware or peripheral software, embedded software is tested by using black-box test based on user scenario for the whole system. This paper suggests the method to coordinate between testing and debugging under consideration for difficulties on solving out the defects detected from black-box test. First of all, from test result analysis, it builds up the debugging strategies enable to trace the locations of the defect's causes. And along with the strategies, it implements the generator of test scripts to be performed on the emulator environment. Through these steps, it can coordinate embedded software testing and debugging activities.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.11
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• pp.2062-2068
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• 2006

In his paper, embedded system implementation for IEEE802.l1p based OFDM-DSRC is presented. After the IEEE802.11p physical layer specification is introduced and BER performance of the modem is evaluated by simulation, implementation aspects of the system such as system architecture, design method and implementation results are addressed. Implemented embedded system for the OFDM-DSRC communication consists of FPGA, flash memory, ARM9 CPU Core, peripherals, etc. from the results, it is shown that the implemented system operates well according to IEEE802.11p specification. It is expected that implemented embedded system shall be used for wireless communication system such as ITS application by enhancing system optimizing.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.136-139
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• 2004

This thesis is realization of embedded system that of MPEG-2 down conversion using IDCT. A method for down conversion of MPEG compressed video is to perform low-pass filtering and sub-sampling after full decompression. However, this method is need large memory and high computational complexity. Recent research has been focussed on the down conversion in the DCT domain. But DCT method is reduced image qualify. The embedded system is require low complexity, and high speed algorithm. When applied to embedded system that down conversion method, DCT method is played average 29 frame per second, and better 25% than spatial-domain down conversion.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.750-751
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• 2012

스마트폰의 급속한 확산과 함께 스마트폰 애플리케이션 시장이 빠르게 성장하고 있다. 이러한 성장세에 따라 많은 애플리케이션 개발자들이 생겨났으며, 다양한 콘텐츠와 수많은 애플리케이션이 개발되어지고 있다. 여기서 우리는 모바일 기기들의 제한적인 요소를 간과해서는 안 된다. 제한적인 모바일기기에서 유저가 만족할 만할 애플리케이션을 개발하기 위해서는 효율적인 자원 활용과 함께 효율적인 프로그래밍을 해야 할 필요가 있다. 본 논문은 안드로이드 NDK 및 SDK를 기반으로 Native C와 Java를 이용해 애플리케이션을 설계하고, 각 애플리케이션간의 알고리즘 수행속도, 프로세서 점유율측면에서 성능측정 실험을 수행했다. 실험 결과를 통해 보다 우수한 성능의 안드로이드 애플리케이션 개발 방법에 관해 연구했다. 성능측정 항목으로는 JNI delay, Integer, Floating point, Memory access algorithm, String이며, 실험은 삼성 갤럭시 S1에서 수행하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Journal of KIISE
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• v.43 no.9
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• pp.998-1007
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• 2016

In recent years, the cost of automotive ECU (Electronic Control Unit) has accounted for more than 30% of total car production cost. However, the complexity of testing and debugging an automotive ECU is increasing because automobile manufacturers outsource automotive ECU production. Therefore, a large amount of cost and time are spent to localize faults during testing an automotive ECU. In order to solve these problems, we propose a fault localization method in memory for developers who run the integration testing of automotive ECU. In this method, memory is partitioned by utilizing memory map, and fault-suspiciousness for each partition is calculated by utilizing memory update information. Then, the fault-suspicious region for partitions is decided based on calculated fault-suspiciousness. The preliminary result indicated that the proposed method reduced the fault-suspicious region to 15.01(%) of memory size.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.