• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.792-802
• /
• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of Korea Multimedia Society
• /
• v.10 no.11
• /
• pp.1446-1459
• /
• 2007

This paper presents and analyzes a novel technique that makes it possible to improve the performance of low-end embedded systems through SoC(System-on-a-Chip) platform supporting dynamic cooperation between hardware and software modules. Traditional embedded systems with limited hardware resources have the poor capability of carrying out multi-tasking jobs including complex calculations. The proposed SoC platform, which provides dynamic cooperation between hardware and software modules, decomposes a single specific system into tasks for given system requirements. Additionally, we also propose a technique for efficient communication and synchronization between hardware and software tasks in cooperation with each other. Several experiments are conducted to illustrate the application and efficiency of the proposed SoC platform. They show that the proposed SoC platform outperforms the traditional embedded system, where only software tasks run, as the number of memory access is increased and the system become more complex.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.11 s.353
• /
• pp.185-191
• /
• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.9
• /
• pp.71-78
• /
• 2008

In this paper, we implement the H.264/AVC baseline decoder by hardware-software partitioning under the embedded Linux Kernel 2.4.26 and the FPGA-based target board with ARM926EJ-S core. We design several IPs for the time-demanding blocks, such as motion compensation, deblocking filter, and YUV-to-RGB and they are communicated with the host through the AMBA bus protocol. We also try to minimize the number of memory accesses between IPs and the reference software (JM 11.0) which is ported in the embedded Linux. The proposed IPs and the system have been designed and verified in several stages. The proposed system decodes the QCIF sample video at 2 frame per second when 24MHz of system clock is running and we expect the bitter performance if the proposed system is designed with ASIC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.888-889
• /
• 2015

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2007.06a
• /
• pp.481-484
• /
• 2007

This paper presents a method of constructing the system-on-chip(SoC) based on embedded systems. The proposed method is more compact and effectiveness than former methods. The requirements generation start high level performance simulation and then passes to an executable specification suitable for implementation using a hardware/software co-design tool. The reuse of pre-exiting components is supported, as well as synthesis of the system interface, but only after much work is done to program the hardware/software co-design tool. The actual design flow described allows feedback among all design levels, e.g. from implementation up to requirements, throughout the process. In the future, it is necessary to development the advanced method of constructing system-on-chip based on embedded systems.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.2 no.1
• /
• pp.24-30
• /
• 2007

According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.11
• /
• pp.2032-2038
• /
• 2007

Embedded Controller which controls whole system is most important part of embedded system. Nowadays, new technique called SoC is more using than ASIC. But SoC have some problems. Because of long development time and high cost, it is hard to applying SoC to small and medium enterprise. So many companies use IP technique combined with embedded processor. High resolution inkjet marking system is printing system with embedded controller. It is used in various part of industry. But it has many problems such as printing quality, marking errors, system faults and so on. In this paper, we designed and implemented IP that can solve the printing quality problems. We analyzed total-logic-elements and timing by simulation. As a result of simulation, we could verified that output signals satisfied reference timing. Appling IP to high resolution inkjet marking system, we could get good quality printing message.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2008.11a
• /
• pp.810-813
• /
• 2008

본 논문에서 연구하고 구현된 JTAG(Joint Test Action Group) Writer는 하나의 SoC(System On a Chip)만 지원하도록 설계된 기존 제품의 단점을 보완할 수 있도록 각 SoC의 제조 회사에서 제공하는 BSDL(Boundary Scan Description Language)을 이용하여 여러 가지 SoC에 쉽게 사용할 수 있도록 모듈화 했다. 그리고 기존 제품들이 사용하고 있는 직렬 포트나 병렬 포트 대신 안정적이고 편리한 USB(Universal Serial Bus) 접속규격을 지원하도록 개선했다.