• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.1
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• pp.10-17
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• 2013

This thesis proposes an automatic embedded core generator system that supports branch prediction. The proposed system includes a dynamic branch prediction module that enhances execution speed of target applications by inserting history/direction flags into BTAC(Branch Target Address Cache). Entries of BHT(Branch History Table) and BTAC are determined based on branch informations extracted by simulation. To verify the effectiveness of the proposed branch prediction module, ARM9TDMI core including a dynamic branch predictor was described in SMDL and generated. Experimental results show that as the number of entry rises, area increase up to 60% while application execution cycle and BTAC miss rate drop by an average of 1.7% and 9.6%, respectively.

• Annual Conference of KIPS
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• 2008.11a
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• pp.843-845
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• 2008

CE (Consumer Electronics) 시장에서 Embedded System 은 time-to-market 이라는 개념이 나날이 중요해 지고 있다. 시스템의 중심인 core processor 에 대하여 지원하는 여러 가지 software toolkit 의 빠른 개발은 무엇보다 중요해지고 있다. 이 논문에서는 GNU Binutils 를 기반으로 ADL 을 이용하여 Embedded system의 core processor 를 위하여 신속한 Assembler 와 Linker 를 개발하는 플랫폼을 개발하였다. 이 플랫폼은 서울대학교 소프트웨어 최적화 연구실에서 개발한 ADL (Architecture Description Language)[1] 을 이용하여 core processor 를 기술하면 자동으로 Assembler 와 Link 를 생성해주는 시스템이다.

• The Journal of Information Technology
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• v.8 no.4
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• pp.91-102
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• 2005

In this paper, development of embedded system based on Windows CE 5.0 which released recently is studied. Embedded softwares for the target board using S3C2410A SOC based on ARM920T core are composed of (1) BSP(Board Support Package) contains an OAL(OEM Adaptation Layer) which includes a boot loader for initializing and customizing target hardware, device drivers, and a corresponding set of configuration files (2) Windows CE 5.0 kernel (3) SDK and MP3 test application. Particularly, PB(Platform Builder) provides the efficient functions to build, test and debug the BSP and CE kernel. It is looked forward to being widely spread that Windows CE 5.0 will be utilized at smart devices such as PMP, CNS and DMB phone which inevitably require a display device.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.35-38
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• 2004

In this paper, we aim to implement the embedded VoIP Phone based on EISC core Microcontroller. EISC is recently new microprocessor architecture, which contains both advantage of RISC and CISC. This advantages are desirably resulted in high code density, high performance and 16/32/64bit scalable instruction length. Also, we select the embedded system which can be guaranteed performance and economical efficiency for implementation that system. As the step of this research, we first study basic system for implementation of target system. Next, we construct the structure of embedded VoIP Phone based on 32bit EISC MCU efficiently. And then we realize that constructed system and verify the performance of that realized system by the test of voice communication in field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.233-236
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• 2003

In this paper, we implement embedded Linux intelligent controller for remote monitoring system. Embedded controller as the hard core is consisted of 32 bit CPU and is designed to have processing of real time monitoring and FFT. The prototype monitoring system can operate with world wide web in GUI environment by java. Detailed design and functional analysis for monitoring system are performed by systems approach.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.526-531
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• 2003

In this paper, we implement embedded Linux intelligent controller and remote monitoring system for Bridge Diagnosis. Embedded controller as the hard core is consisted of 32 bit CPU and is designed to have processing of real time monitoring and FFT for Bridge Diagnosis. The prototype monitoring system can operate with world wide web in GUI environment by Java. Detailed design and functional analysis for monitoring system are performed by systems approach.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.223-223
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• 2000

Embedded system area has brought an innovation and has been spread rapidly by the growth of the Internet, wireless telephony and multimedia recently. Many embedded systems are required to be real-time systems in that it needs multi-tasking and priority based scheduling. This paper introduces a real-time system that was developed with web server ability for control and monitoring system employing a real-time operating system. It discusses the design model, structure, and applications of web server system. We used SNDS100 board which has a 32-bit RISC microcontroller of ARM7TDMI core as a hardware platform. MicroC/OS kernel was used as Real-time operating system that supports a preemptive and multitasking functions. We developed a hierarhchical control and monitoring system that not only reduced system and management costs, but also enhanced reusability and portability.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.3
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• pp.268-273
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• 2005

We propose the specialized product-line development methodology for developing the embedded system of an MSDFS (Multi Sensor Data Fusion System : called MSDFS). The product-line methodology provides a simultaneous design between software and hardware, high level reusability. However this is insufficient in requirement analysis stage due to be focused on software architecture, detailed design and code. Thus we apply the business model based on IDEF0 technique to traditional methodology. In this paper, we describe the processes of developing Core-Asset, which are requirement analysis, feature modeling, validation. The proposed model gives the efficient result for eliciting features, and ensures the high level reusability of modules performing on embedded system.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.30 no.7
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• pp.27-33
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• 2012

• Journal of Korea Multimedia Society
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• v.17 no.3
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• pp.324-332
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• 2014

This paper presents a programmable System-On-a-chip for various embedded applications that need Neural Network computations. The system is fully implemented into Field-Programmable Gate Array (FPGA) based prototyping platform. The SoC consists of an embedded processor core and a reconfigurable hardware accelerator for neural computations. The performance of the SoC is evaluated using real image processing applications, such as optical character recognition (OCR) system.