• Proceedings of the KIEE Conference
• /
• 2003.11c
• /
• pp.998-1001
• /
• 2003

In this paper, a entertainment biped robot controlled by R/C servo motors is built using the embedded RTOS (Real Time Operating System). uC/OS-II V2.00 is used for RTOS and control algorithm of R/C servo motors is proposed based on uC/OS-II's preemptive and deterministic property without any extra PWM module. The realized biped robot has 19 DOF, and a board 80C196KC as main CPU. To verify the proper walking process, ZMP(Zero Moment Point) theory is applied and ADAMS is used for simulation.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06c
• /
• pp.57-59
• /
• 2012

전자지불 임베디드 시스템의 DB는 목적 및 기능에 따라 다양하며 비용을 최소화 하기 위해 CPU, Memory, Storage 등이 범용 PC와 비교하여 낮은 성능을 가진다. 이와 같은 특징으로 인해 범용 database을 임베디드 환경에서 사용하는 경우, 요구 성능을 만족하지 못할 수 있다. 본 논문에서는 자체 구현한 전자지불 임베디드 환경에서 전자카드 리스트 관리 데이터 베이스 엔진(이하 DBX)와 임베디드 DB 중 Berkeley DB, SQLite와 함께 성능을 측정하고 해당 결과를 분석하였다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2010.04a
• /
• pp.72-74
• /
• 2010

임베디드 시스템은 하드웨어 리소스가 매우 작다. CPU속도가 느리고 메모리 크기도 작다. 이런 환경에서의 소프트웨어는 최적화된 크기를 가지고 수행속도가 빠르며 병목 현상이 없어야한다. 이렇게 코드를 최적화하기 위해서는 현재 코드의 문제를 찾아내야 한다. 이것은 정적 분석으로 만으로는 부족하고 프로그램을 수행시켜가면서 정보를 수집하는 프로파일러가 필요하다. 기존의 프로파일러는 윈도우, 리눅스 상에서 수행되는 응용프로그램을 위한 것이기 때문에 저급 임베디드 시스템에서 프로파일러를 수행할 수 없다. 본 논문에서는 이러한 문제를 해결하기 위해서 임베디드용 프로파일러를 설계 및 구현 한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.344-345
• /
• 2011

본 논문에서는 영상처리를 이용해서 물품을 색상별로 분류하는 로봇 개발에 대해 기술한다. 그동안 로봇에서 획득한 영상 데이터를 고성능 host PC에 보내어 처리하고 로봇은 그 결과만을 받아 사용하는 것이 일반적이었으나, 최근에는 embedded CPU의 비약적인 발전에 따라 영상을 로봇 자체에서 영상 처리 하는 것이 점점 더 용이해지고 있다. 따라서 본 논문에서 기술하는 색상별 물체 분류기 로봇 개발을 통하여 로봇에서의 영상 처리 가능성을 알아보고자 한다.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2004.10a
• /
• pp.742-745
• /
• 2004

If a personal robot is popularized like a personal computer in the future, many kinds of robots will appear and the number of manufacturers will increase as a matter of course. In such circumstances, it can be inefficient, in case each manufacturer makes a whole platform individually. The solutions for this problem are to modularize a robot component (hardware and software) functionally and to standardize each module. Each module is developed and sold by each special maker and a consumer purchases desired modules and integrates them. The standardization of a module includes the unification of electrical and mechanical interface. In this paper, the standard interfaces of modules are proposed and CMR(Component Modularized Robot)-P2 made with the modules(brain, sensor, mobile, arm) is introduced. In order to simplify and to make the modules light, a frame is used for supporting a robot and communication/power lines. The name of a method and the way to use that are defined dependently on the standard interfaces in order to use a module in other modules. Each module consists of a distributed object and that can be implemented in the random language and platform. The sensor, mobile and arm modules are developed on Pentium or ARM CPU and embedded Linux OS using the C programming language. The brain module is developed on Pentium CPU and Windows OS using the C, C++ and RPL(Robot Programming Language). Also tasks like pass planning, localization, moving, object perception and face perception are developed. In our test, modules got into gear and CMR-P2 executed various scenarios like guidance, errand and guarding completely.

• Journal of the Korea Computer Industry Society
• /
• v.4 no.4
• /
• pp.547-552
• /
• 2003

In this thesis, interference phenomena of bluetooth networks requiring Security were minimized; strengthened security of piconet by assigning an identical PIN code to bluetooth devices, which was establishing a specific piconet during authentication stage. To establish a bluetooth piconet system. an unique ID was assigned to each bluetooth device, communication algorithms having different data formats between devices was designed, and an embedded hardware module using ARM processor and uCOS-II RTOS was implemented. About 30% of CPU efficiency in the module was increased by modifying functions including block parameters to work as nonblocking; by the increased efficiency of total piconet, the module could be used as an access point. The module could transmit maximum 10 frames of image and also audio signal by switching the packet effectively according to channel condition. By above-mentioned process, video, audio, and data could be well transmitted by the bluetooth managing program and the possibility of a commercial remote control system using bluetooth technology was suggested.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.9 no.5
• /
• pp.1139-1144
• /
• 2008

In this paper, we propose an automatic generation method of transaction level(TL) model from algorithmic model to verify system specification fast and effectively using virtual platform. The TL virtual platform including structural properties such as timing, synchronization and real-time is one of the effective verification frameworks. However, whenever change system specification or HW/SW mapping, we must rebuild virtual platform and additional design/verification time is required. And the manual description is very time-consuming and error-prone process. To solve these problems, we build TL library which consists of basic components of virtual platform such as CPU, memory, timer. We developed a set of design/verification tools in order to generate a virtual platform automatically. Our tools generate a virtual platform which consists of embedded real-time operating system (RTOS) and hardware components from an algorithmic modeling. And for communication between HW and SW, memory map and device drivers are generated. The effectiveness of our proposed framework has been successfully verified with a Joint Photographic Expert Group (JPEG) and H.264 algorithm. We claim that our approach enables us to generate an application specific virtual platform $100x{\tims}1000x$ faster than manual designs. Also, we can refine an initial platform incrementally to find a better HW/SW mapping. Furthermore, application software can be concurrently designed and optimized as well as RTOS by the generated virtual platform

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.10
• /
• pp.190-196
• /
• 2014

This paper proposes a mobile-optimized pedestrian detection method using Cascade of HOG(Histograms of Oriented Gradients) for ADAS(Advanced Driver Assistance System) on smartphones. In order to use the limited resource of mobile platforms efficiently, the method is implemented by the OpenCL(Open Computing Language) library, and its processing time is reduced in the following two aspects. Firstly, the method sets a program build option specifically and adjusts work group sizes as variety of kernels in the host code. Secondly, it utilizes local memory and a LUT(Look-Up Table) in the kernel code to accelerate the program. For performance evaluation, the developed algorithm is compared with the mobile CPU-based OpenCV(Open Computer Vision) for Android function. The experimental results show that the processing speed is 25% faster than the OpenCV hogcascade.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.44-53
• /
• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• The Journal of the Korea Contents Association
• /
• v.10 no.3
• /
• pp.64-71
• /
• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.