• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.95-95
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• 2008

본 연구에서는 SiGe p-MOSFET을 제작하여 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성을 측정하였다. Si 기판위에 성장한 $Si_{0.88}Ge_{0.12}$으로 제작된 SiGe p-MOSFET의 채널은 게이트 산화막과 20nm 정도의 Si Spacer 층으로 분리되어 있다. 게이트 산화막은 열산화에 의해 70$\AA$으로 성장되었고, 게이트 폭은 $25{\mu}m$, 게이트와 소스/드레인 사이의 거리는 2.5때로 제작되었다. 제작된 SiGe p-MOSFET은 빠른 동작 특성, 선형성, 저주파 노이즈 특성이 우수하였다. 제작된 SiGe p-MOSFET의 ESD 에 대한 소자의 신뢰성과 내성을 연구하기 위하여 SiGe P-MOSFET에 ESD를 lkV에서 8kV까지 lkV 간격으로 가한 후, SiGe P-MOSFET의 I-V 특성과 게이트 길이, $V_D$, $V_G$의 변화에 따른 저주파 노이즈특성 변화를 분석 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.601-607
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• 2015

A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

• Proceedings of the Optical Society of Korea Conference
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• 2008.02a
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• pp.93-94
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• 2008

In order to suppress the current crowding in light emitting diodes (LEDs) grown on sapphire substrate, the effect of nonuniform contact resistivity between TME layer and p-GaN layer on the LED surface was theoretically investigated. The analysis results showed that current crowding occurring around p-electrode could be considerably improved, which in turn would be helpful to improve the electrostatic discharge (ESD) characteristic.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.27-32
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• 2016

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

• Journal of the Korean Society of Safety
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• v.34 no.5
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• pp.37-45
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• 2019

The characteristic of fire and explosion related to electrostatic discharge is that it is difficult to reproduce the electrostatic charge and discharge phenomenon in addition to the large human and material damage. Therefore, in order to prevent accidents and disasters related to electrostatic in fire and explosion hazard areas, it is important to manage the level of electrostatic in a safe manner from the perspective of system between industrial facilities and human bodies. Rule 325 of the Occupational Safety and Health Regulations, "Prevention of Fire / Explosion due to Electrostatic", requires the use of grounding, conductive materials, humidification and electrification in order to prevent the risk of disaster caused by static explosion and electrostatic in the production process. In order to comply with these measures, related technologies, standards and systems are needed from the viewpoint of preventive measures related to electrostatic in fire and explosion hazard areas, but in Korea, it is still insufficient. Therefore, technical, institutional and managerial measures are needed as a precautionary measure to improve the level of ESD safety in fire and explosion hazard areas and prevent electrostatic related injury. In Korea, we analyzed the current status and characteristics of electrostatic related disaster by using the statistics of industrial accident and fire statistics of the Ministry of Employment and Labor. We also analyzed the current status and characteristics of electrostatic related disasters in Japan using JNIOSH accidents and disasters investigation cases and JNIOSH fire accident data of Japan Fire Bureau. The purpose of this study is to compare and analyze the current status of electrostatic related accidents and disasters in Korea and Japan in order to improve the safety management of electrostatic in fire and explosion hazard areas. In order to prevent accidents and disasters in the industrial field, The technical, institutional, and managerial measures to manage the level of electrostatic in a safe state were derived from the system point of view.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1429-1435
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• 2004

In this work, high performance broadband amplifier MMIC including all the matching and biasing components, and electrostatic discharge (ESD) protection circuit was developed for K/Ka band applications. Therefore, external biasing or matching components were not required for the operation of the MMIC. STO (SrTiO3) capacitors were employed to integrate the DC biasing components on the MMIC, and miniaturized LC parallel ESD protection circuit was integrated on MMIC, which increased ESD breakdown voltage from 10 to 300 V. A pre-matching technique and RC parallel circuit were used for the broadband design of the amplifier MMIC. The amplifier MMIC exhibited good RF performances and good stability in a wide frequency range. The chip size of the MMICs was $1.7{\pm}0.8$ mm2.