• Journal of Power Electronics
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• v.10 no.4
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• pp.434-443
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• 2010

A general purpose experimental set-up has been designed and implemented for students to carry out various experiments on inverters in the power electronics laboratories of universities, during a few hours of laboratory work. This is the first inverter setup that incorporates hardware and software control, as well as an optional user interface in a laboratory experimental set-up of a single multi-purpose inverter, thus making the system versatile and very practical for both undergraduate and graduate students. The system can be controlled either by a computer or through a liquid crystal display (LCD) and a keypad control unit, and it constitutes a low-cost alternative to relatively expensive commercial teaching sets. The computer provides a user friendly interface and easier control for laboratory environments equipped with computers. The LCD and keypad units eliminate the need for a computer, which makes this system usable in the laboratory as a standalone unit as well.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.5
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• pp.311-318
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• 2019

In general wireless power transfer systems (WPTSs), power transfer is controlled by the wireless communication between a transmitter (Tx) and a receiver (Rx). However, WPTS is difficult to apply in electronic products that do not have batteries, such as TVs. A WPTS with resonators based on a transformer of LLC series resonant converter is proposed in this study to eliminate wireless communication units between a Tx and an Rx. The proposed system operates at the boundary of the resonance frequency, and the required power can be stably supplied to authorized devices even though some misalignment occurs. Moreover, standby power standards for the electronic product can be satisfied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1097-1099
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• 1987

This paper describes a method which detects the phrase and clause in Korean sentences. By analysing modificatory relation of modifier and modified word in Korean, two rules are defined. (1) The rules of phrase and clause. (2) The rules of separation points. As the result of this method, the conceptual units are easily elicited from the Korean sentence.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.7
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• pp.1-7
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• 1997

VHDL simulation requires both analysis and elaboration processes. Reducing the time taken by these processes shorten design cycles. We propose an incremental analysis and elaboration algorithm for VHDL, which minimizes the number of design units to be re-analyzed and re-elaborated after an incremental change, thereby reducing the desing cycle time. Experimental results show about four times performance improvement in analysis and 1.25 times in elaboration over the conventional method.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1149-1152
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• 2002

This paper presents the computerised simulation of colour-blindness and proposes a colour enhancement technique to aid colour-blinded people to use Visual Display Units (VDU). With the red-green colour perception difficulties, the ISH model has been used to develop the algorithms. The simulator and colour enhancement have been tested by colour-blind people and compared to existing simulators for colour-blindness.

• Electronics and Telecommunications Trends
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• v.25 no.4
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• pp.69-82
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• 2010

과거 단순한 이동 수단이 목적이었던 자동차는 더욱 안전하고 편리한 자동차, 서비스 지향 자동차로 거듭나고 있다. 점차 편리와 안전 서비스를 제공하기 위한 전자제어 장치의 장착이 확대되고 전자제어 장치간의 연동을 통한 서비스 개발이 늘고 있으며, 이로 인해 신뢰성 빛 안전성 이슈가 최근에 많이 대두되고 있다. 본 고에서는 자동차 응용 서비스의 개발에서 IT 기술들의 집합체라고 할 수 있는 전자장치용 소프트웨어의 표준 플랫폼인 AUTOSAR의 동향과 차량 전자제어 장치의 안전성 보장을 위한 ISO 26262 표준 동향 및 이슈를 살펴본다.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.6
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• pp.1-10
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• 1997

This paper presents an adaptive optimal learning controller for uncertian robot systems which makes use fo simple DNN(dynamic neural network) units to estimate uncertain parameters and learn the unknown desired optimal input. With the aid of a lyapunov function, it is shown that all that error signals in the system are bounded and the robot trajectory converges to the desired one globally exponentially. The effectiveness of the proposed controller is hsown by applying the controller to a 2-DOF robot manipulator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.4
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• pp.652-657
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• 1987

This paper describes an application of CMOS Gate Array Integrated Cricuits to the implementation of three functional units: A Multiplexer, Time Switch, and Demultiplexer in the Switching Network and Digital Line Concentrator of TDX-1 system, which is a fully digital time division electronic switching system in Korea. The application of CMOS Gate Array Integrated Circuits significantly improves the overall system performance in terms of power consumption, cost, size, reliability, and timing margin, etc.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.119-124
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• 1988

Real-time adaptive lattice predictor was implemented on the TMS32020 DSP chip for digital signal processing. The implemented system was composed of Input-Output units and centrla processing-control unit and its supporting assembly soft ware. The performance of hardware realization was verified by comparing input signal and one-step prediction signal which are calcualted by the real-time adaptive lattice predictor. As a result, for 4 stage lattice structure, the maximum running frequency was obtained as 6.41 KHz in this experiment.