• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.43-52
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• 1997

Processors using the superscalar rchitecture can achieve high performance by executing multipel instructions in a clock cycle. It is made possible by having multiple functional units and issuing multiple instructions to functional units simultaneously. But instructions can be dependent on one another and these dependencies prevent some instructions form being issued at the same cycle. In this paper, we designed an issue unit of a superscalar RISC microprocessor that can issue four instructions per cycle. The issue unit receives instructions form a prefetch unit, and issues them in order at a rate of as high as four instructions in one cycle for maximum utilization of functional units. By using an instruction buffer, the unit decouples instruction fetch and issue to improve instruction ussue rate. The issue unit is composed of an instruction buffer and an instruction decoder. The instruction buffer aligns and stores instructions from the prefetch unit, and sends the earliest four available isstructions to the instruction decoder. The instruction decoder decodes instructions, and issues them if they are free form data dependencies and necessary functional units and rgister file prots are available. The issue unit is described with behavioral level HDL (lhardware description language). The result of simulation using C programs shows that instruction issue rate is improved as the instruction buffer size increases, and 12-entry instruction buffer is found to be optimum considering performance and hardware cost of the instruction buffer.

• Journal of Power Electronics
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• v.14 no.5
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• pp.946-956
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• 2014

Cascaded H-Bridge (CHB) converters can be directly connected to medium-voltage grids without using transformers and they possess the advantages of large capacity and low harmonics. They are significant tools for providing grid connections in large-capacity renewable energy systems. However, the reliability of a grid-connected CHB converter can be seriously influenced by the number of power switching devices that exist in the structure. This paper proposes a fault-tolerant control strategy based on double zero-sequence voltage injection and DC voltage optimization to improve the reliability of star-connected CHB converters after one or more power units have been bypassed. By injecting double zero-sequence voltages into each phase cluster, the DC voltages of the healthy units can be rapidly balanced after the faulty units are bypassed. In addition, optimizing the DC voltage increases the number of faulty units that can be tolerated and improves the reliability of the converter. Simulations and experimental results are shown for a seven-level three-phase CHB converter to validate the efficiency and feasibility of this strategy.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.1
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• pp.11-22
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• 1994

For the conventional systme based on word, it is very difficult to enlarge the number of vocabulary. To cope with this problem, we must use more fundamental units of speech. For example, syllables and phonemes are such units, Korean speech consists of initial consonants, middle vowels and final consonants and has characteristic that we can obtain syllables from speech easily. In this paper, we show a speech recognition system with the advantage of the syllable characteristics peculiar to the Korean speech. The algorithm of recognition system is the Time Delay Neural Network. To recognize many recognition units, system consists of initial consonants, middle vowels, and final consonants recognition neural network. At first, our system recognizes initial consonants, middle vowels and final consonants. Then using this results, system recognizes isolated words. Through experiments, we got 85.12% recognition rate for 2735 data of initial consonants, 86.95% recognition rate for 3110 data of middle vowels, and 90.58% recognition rate for 1615 data of final consonants. And we got 71.2% recognition rate for 250 data of isolated words.

• Proceedings of the SAREK Conference
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• 2005.11a
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• pp.427-432
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• 2005

This study developed a program for detecting charged refrigerant amount in system air-conditioner. System air-conditioner is an air-conditioning system with multiple indoor units. Due to the complexity of the system, it is more difficult to detect the refrigerant amount charged in system air-conditioner than in a general single air-conditioner. Experiments were performed for 6 HP outdoor units with 3 indoor units in a psychrometric calorimeter. The experimental amount of charged refrigerant were ranged from 60% to 140% with 10% increasement. Fuzzy algorithm were emploeed for detecting the charged refrigerant amount in a system air-conditioner. The experimental data were used for curve fitting for general ranges for indoor and outdoor temperature conditions. membership function were determined for whole ranges of experimentally measured data and rulebase were defined for each amount of refrigerant charge. Developed program successfully predicted the measured data within 10% resolution range.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.837-840
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• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.4
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• pp.82-87
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• 2010

Modern GPUs(Graphic Processing Units) provide computing capability higher than that of the general CPUs(Central Processor Units). With supports of programmability of graphics pipeline GP-GPU(General Purpose computation on GPU) has gained much attention expanding its application area. This paper compares sequential and massively parallel implementations of FDTD(Finite Difference Time Domain) algorithm using CUDA(Compute Unified Device Architecture). Experimental results show upto 45X speedup over conventional CPU execution.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.321-324
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• 2002

Nowadays variable delay arithmetic units have been used for implementing a datapath of\ulcorner target system in pursuit of performance improvement. However. adoption of variable delay arithmetic units requires modification of a typical synchronous control units design methodology. There is a representative approach, which is called a monolithic approach. Although its results are good, its proposed methodology may cause critical problems in the aspects of area and performance with the size increase of initial system specifications. In order to solve this problems, a distributed approach is suggested. Experimental results show that the Proposed method can guarantee original performance of an initial system specification with minimized additional area increase.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.458-463
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• 1998

The paper describes the methods and means of measurement and study of vibrations, stresses and shocks affecting electronic equipment during its use and in the testing stage as well as original units to determine shapes and frequencies of vibrations of functional boards. Particular attention has been given to the development of methods and means to protect sturctures against vibrations and shocks.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.11
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• pp.705-715
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• 2016

In this study, the cycle performance of an air conditioner with multi-indoor units is analyzed and simulated. The cycle performance could be predicted through the integration of mathematical formulation for these devices. The condenser pressure is obtained by an iteration process to match the mass flow rates of the compressor and the expansion valve and the evaporator pressure is determined by an iteration process, in which the suction super heat is tracing the targeted super heat. The required software was developed by system programming. the software algorithm is extended to predict the cycle performance of an air conditioner system with multi-indoor units, and then the numerical results are compared with experimental results. This mathematical model is validated from the result of experiments conducted on 8.3kW air conditioner. The errors in capacity, electronic power, and COP are found to be within 10% in general.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.