• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7C
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• pp.705-711
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• 2003

This paper studies the application of a fuzzy-ARTMAP neural network to digital communications channel equalization. This approach provides new solutions for solving the problems, such as complexity and long training, which found when implementing the previously developed neural-basis equalizers. The proposed fuzzy-ARTMAP equalizer is fast and easy to train and includes capabilities not found in other neural network approaches; a small number of parameters, no requirements for the choice of initial weights, automatic increase of hidden units, no risk of getting trapped in local minima, and the capability of adding new data without retraining previously trained data. In simulation studies, binary signals were generated at random in a linear channel with Gaussian noise. The performance of the proposed equalizer is compared with other neural net basis equalizers, specifically MLP and RBF equalizers.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.30-36
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• 1990

Context-free language can be recognized by Cocke-Younger-Kasami algorithm. This algorithm is a class of polyadic-nonserial dynamic programming technique and has the O(n**3) time complexity. In this paper, a one-dimensional systolic array for recognition of context-free language is designed. The designed triangle type two-dimensional array is projected and transformed to an one-dimensional array. The designed one-dimensional array has n processing elements and \ulcornern+1)/2\ulcorner(n-1)+3n-1 time units to process the algorithm (n is the length of input string). The time complexity is O(n\ulcorner.

• Journal of the Korea Society of Computer and Information
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• v.5 no.2
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• pp.158-164
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• 2000

The purpose of this study is concerned with evaluating management performance in electronics and communication companies using DEA(Data Envelopment Analysis) DEA is a linear programming based technique for measuring the relative performance of organizational units where the Presence of multiple inputs and outputs makes comparisons difficult. In this research. input variables are raw-material costs, number of employees, and production capacity Real production, sales revenue and net earning are suggested as output variables. Management performance of most companies are increased or equal during 97 and 98 fiscal year and input & output variables show high correlation.

• Current Optics and Photonics
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• v.4 no.3
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• pp.186-192
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• 2020

This paper describes a real-time monitoring system in Ethernet passive optical networks (EPON) that uses burst-mode fiber Bragg grating (FBG) optical sensors. The FBG interrogation unit in the optical line terminal (OLT) transmits the monitoring wavelength to optical network units (ONUs). The FBG sensor unit in each ONU returns a burst-mode monitoring signal to the OLT. As the system applies time division multiple access (TDMA), a uniform Bragg wavelength can be used to monitor the EPON system. The FBG interrogation unit analyzes the received burst-mode monitoring signals and outputs fault information on the ONU branches in EPON. The simulation results show the effectiveness of the proposed monitoring system based on TDMA. In addition, we compared the proposed TDMA-based monitoring system with a WDMA-based monitoring system.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.7
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• pp.1015-1024
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• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.5
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• pp.21-30
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• 1973

A snaked-line array antenna is investigated for the use of high gain antenna at X-band frequency by studing its attenation constant and the radiation pattern. Attenuation constant which is equivalent to the radiation resistance varies roughly as a function of the square of sinh$\theta$a where sin$\theta$a corresponds to the amplitude of sinusoidal form of snaked-line. The directivity is determined by the number of snaked-line antennas and the periodic units of a snaked line.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.1-10
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• 1997

By considering low power design at higher levels of abstraction rather than at lower levels of abstraction, we can apply various transformation techniques to a system design with wider view and obtain much more effective power reduction with less cost and effort. In this paper, a transformation technique, called power - conscious loop folding is proposed for high level synthesis of a low power system.Our work is focused on reducing the power consumed by functional units in adata path dominated circuit through the decrease of switching activity. Te transformation algorithm has been implemented and integrated into HYPER, a high level synthesis system for experiments. In our experiments, we could achieve a pwoer reduction of up to 50% for data path dominated circuits.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.323-325
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• 1996

The design of Intelligent Energy Saving Power System Controller (IESPSC) for Telecom DC power plants is proposed and presented in this paper. From the past experience. rectifiers for Telecom DC power plants have been operated inefficiently at light loads. IESPSC offers "novel load sharing" approach based on the knowledge of each unit's efficiency of paralleled rectifiers. Neural networks is used for identifying each rectifier's efficiency characteristic curve corresponding to load currents, which is in turn utilized to produce a system efficiency close to the maximum under all operating conditions. In addition, by limiting the number of operating units to the minimum while maintaining high efficiency at the determined loads, a drastic savings in operating cost can be achieved.

• Journal of Power Electronics
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• v.15 no.4
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• pp.920-928
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• 2015

Transformerless solar inverters have a higher efficiency than those with an isolation link. However, they suffer from a leakage current issue. This paper proposes a family of single phase six-switch transformerless inverter topologies with an ac bypass circuit to solve the leakage current problem. These circuits embed two unidirectional freewheeling current units into the midpoint of a full bridge inverter, to obtain a freewheeling current path, which separates the solar panel from the grid in the freewheeling state. The freewheeling current path contains significantly fewer devices and poor performance body diodes are not involved, leading to a higher efficiency. Meanwhile, it is not necessary to add a voltage balancing control method when compared with the half bridge inverter. Simulation and experiments are provided to validate the proposed topologies.