• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.212-212
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• 2008

에폭시 수지는 화학적 열적 안정성과 절기 절연성 및 기계적 특성 등 여러 가지 우수한 특성에도 불구하고 난연성은 그 단독으로 만족시킬 수 없기 때문에 난연제를 첨가함으로써 난연효과를 얻어왔다. 기존에 할로겐 화합물인 브롬계 난연제는 우수한 난연효과에도 불구하고 연소시 유해물질이 발생되어진다. 그리하여 인계 난연제를 첨가하는 것이 고분자 시스템에 난연성을 부여하는 효과적인 수단으로 대두되어지고 있다. 이 실험에서는 인계 난연제와 브롬계 난연제를 10, 20, 30, 40wt% 첨가하여 epoxy composite 제작하였다. 제작된 epoxy composite를 UL-94V 방법으로 난연성 평가하여 브롬계 난연제 20wt%에서 V-0를 획득할 수 있었으나 인계난연제 40wt%에서도 V-0를 만족할 수 없었다. 난연제 함량에 따른 Dielelctric constant 및 loss는 브롬계 난연제를 첨가시 감소하였고, 인계난연제의 경우 증가하였다.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.1-5
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• 2015

In high temperature aircraft electronics, aluminium based brazing filler is the prime choice today. Aluminium and its alloys have compatible properties like weight minimization, thermal conductivity, heat dissipation, high temperature precipitation hardening etc. suitable for the aerospace industry. However, the selection of brazing filler for high temperature electronics requires high temperature joint strength properties which is crucial for the aerospace. Thus the selection of proper brazing alloy material, the composition and brazing method play an important role in deciding the final reliability of aircraft electronic components. The composition of these aluminium alloys dependent on the addition of the various elements in the aluminium matrix. The complex shapes of aluminium structures like enclosures, heat dissipaters, chassis for electronic circuitry, in avionics are designed from numerous individual components and joined thereafter. In various aircraft applications, the poor strength caused by the casting and shrinkage defects is undesirable. In this report the effect of various additional elements on Al based alloys and brazing fillers have been discussed.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2000년도 춘계학술발표대회 논문집
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• pp.175-183
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• 2000

The internal residual stresses within the multilayered structure with shan interface induced by the difference in thermal expansion coefficient between the materials of adjacent layers often provide the source of failure such as delamination of interfaces and etc. Recent development of the multilayered structure with functionally graded interface would be the solution to prevent this kind of failure. However a systematic thermo-mechanical analysis is needed fur the customized structural design of multilayered structure. In this study, theoretical model for the thermo-mechanical analysis is developed for multilayered structures of the Al-$SiC_p$ functionally graded composite for electronic packaging. The evolution of curvature and internal stresses in response to temperature variations is presented for the different combinations of geometry. The resultant analytical solutions are used for the optimal design of the multilayered structures with functionally graded interface as well as with sharp interface.

• 한국전기전자재료학회논문지
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• 제28권8호
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• pp.524-530
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• 2015

We propose a three-electrode type electronic paper display and its fabrication process to realize single color at the same display panel. We establish a fabrication process with the mixing of electronic ink, loading of this ink, electronic ink assembly, packaging and driving. Also, we discuss an operating principle of this panel and the induced image reversal phenomenon by electric field area of the lower electrodes. This phenomenon is not occurred for the panel having $10{\mu}m$ electrode space. By this pixelation structure like this three-electronic paper display, a single color realization without color filter is possible and various kind of color is defined by a dye selection for charged particles and electrically neutral fluid.

• 대한기계학회논문집
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• 제18권8호
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• pp.2158-2166
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• 1994

In order to understand the package crack emanating from the edge of leadframe after the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the M-integral and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the package crack are investigated taking into account the temperature dependence of the material properties, which simulates a more realistic condition. If the temperature dependence of the material properties is considered the result of analysis conforms with observations that the crack is kinked at between 50 and 65 degree. However, in case of constant material properties at the room temperature it is found that the J-integral is underestimated and the kink crack angle is different form the observation. The effects of the material properties and molding process temperature on J-integral and crack angle are less significant that the chip size for the cases considered here. It is suggested that the geometric factors such as ship size, leadframe size are to be well designed in order to prevent(or control) the occurrence and propagation of the package crack.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional Pt layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at $330^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.332-336
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• 2001

In this study, the reaction at UBM(Under Bump Metallurgy) and solder interface was investigated. The UBM employed in conventional optical packages, Au/Pt/Ti layer, were found to dissolve into molten Au-Sn eutectic solder during reflow soldering. Therefore, the reaction with different diffusion barrier layer such as Fe, Co, Ni were investigated to replace the conventional R layer. The reaction behavior was investigated by reflowing the solder on the pad of the metals defined by Cr layer for 1, 2, 3, 4, and 5 minutes at 330$^{\circ}C$. Among the metals, Co was found to be most suitable for the diffusion barrier layer as the wettability with the solder was reasonable and the reaction rate of intermetallic formation at the interface is relatively slow.

• 마이크로전자및패키징학회지
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• 제26권3호
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• pp.63-69
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• 2019

전자부품에 대한 보드실장은 아직까지 솔더를 이용한 접합기술을 주로 이용하고 있다. 그러나, 솔더의 크? 및 피로특성으로 인한 접합부 내구한계로, 자동차 전장모듈에서는 반영구적인 접합기술인 프레스 핏(Press-fit) 접합기술 적용을 확대하고 있다. 프레스 핏 접합은 프레스 핏 금속단자를 보드내 쓰루 홀(Through hole)에 기계적으로 삽입하여 체결하는 접합기술로써, 적절한 금속단자의 소성변형으로 쓰루 홀 내부 표면접합을 밀착시킴으로써 강건한 접합을 유도한다. 본 논문에서는 보드내 쓰루 홀 크기 및 표면처리에 따른 프레스 핏 접합 특성 및 신뢰성을 솔더링과 함께 비교하기 위해, 보드 쓰루 홀 크기에 따른 삽입강도 및 삽발강도를 평가하였으며, 열충격 시험을 통한 실시간 저항변화를 통해 프레스 핏 및 솔더링 접합부의 저항변화를 관찰하였다. 또한, 각 접합부위 분석을 통한 프레스 핏 및 솔더링 접합열화를 분석하여 주요 파손모드를 고찰하고자 하였다.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.5-8
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• 2009

In this paper, a high-quality low-temperature co-fired ceramic (LTCC) solenoid inductor using a solder ball and an air cavity on a silicon wafer for three-dimensional (3-D) system-in-package (SiP) is proposed. The LTCC multi-layer solenoid inductor is attached using Ag paste and solder ball on a silicon wafer with the air cavity structure. The air cavity is formed on a silicon wafer through an anisotropic wet-etching technology and is able to isolate the LTCC dielectric loss which is equivalent to a low k material effect. The electrical coupling between the metal layer and the LTCC dielectric layer is decreased by adopting the air cavity. The LTCC solenoid inductor using the solder ball and the air cavity on silicon wafer has an improved Q factor and self-resonant frequency (SRF) by reducing the LTCC dielectric resistance and parasitic capacitance. Also, 3-D device stacking technologies provide an effective path to the miniaturization of electronic systems.