• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1092-1095
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• 2001

Steady state thermal analysis has been done by a finite element method in a diode of 12kV blocking voltage. The diode was fabricated by soldering ten pieces of 1200V diodes in series, capping a dummy wafer at the far end of diode series, and finally wire bonded for building anode and cathode terminal. In order to achieve high voltage and reliability, the edge of each diode was beveled and passivated by resin with a thickness of 25${\mu}$m. It was assumed that the generated heat which is mainly by the on-state voltage drop, 9V for 12kV diode, is dissipated by way of the conduction through diodes layers to bonding wire and of the convection at the surface of passivating resin. It was predicted by the thermal analysis that the temperature rise of a pn junction of the 12kV diode can reach at the range of 16∼34$^{\circ}C$ under the given boundary conditions. The thickness and thermal conductivity(0.3∼3W/m-K) of the passivating resin did little effect to lower thermal resistance of the diode. As the length of the bonding wire increased, which means the distance of heat conduction path became longer, the thermal resistance increased considerably. The thermal analysis results imply that the generated heat of the diode is dissipated mainly by the conduction through the route of diode-dummy wafer-bonding wire, which suggests to minimize the length of the wire for the lowest thermal resistance.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.11
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• pp.3538-3548
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• 1996

In this study, as a part of basic study for developing the simulation program for the assemssment of reliability of electronic EMC packaging which covers from EMC mixing step to thermal analysis, comparison between a measured and predicted values of material properties of EMC and finitde element analysis of thermal stress are performed. For the experimental testing specimens of fifty, sixty hive and eighty percent filler($13\mu m$, spherical silica) weight fraction are fabricated using tranfer molding. Coefficient of thermal expansion, elastic modulus and thermla conductivity are measured using these specimens and then these measured values are compared with the predicted values by various equations ( such as dilute suspension method. self consistent method, generalized self consistent method, Hashin-Shtrikman's bounds. Shapery's bounds, Nielsen's method and others). Measured values are distributed within the upper and lower bounds of equations. Measured elastic modulus and coefficient of thermal expansion approaches closely the perdicted values with self consisten mehtod and upper bound of Shaperys equation respectively. However small differences of thermal conductivity between the different filler volume fraction are obserbed. FEM analysis indicates that firstly stress is concentrated at the corner section of EMC and secondly EMC with eighty percent filler weight fraction shows less thermal stress when package is cooling down and relatively high thermal stress when package is heating up.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.23-29
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• 2013

Development of flexible electronic devices has primarily focused on printing technology using organic materials. However, organic-based flexible electronics have several disadvantages, including low electrical performance and long-term reliability. Therefore, we fabricated nano- and micro-thick silicon film attached to the polymer substrate using transfer printing technology to investigate the feasibility of silicon-based flexible electronic devices with high performance and high flexibility. Flexibility of the fabricated samples was investigated using bending and stretching tests. The failure bending radius of the 200 nm-thick silicon film attached on a PI substrate was 4.5 mm, and the failure stretching strain was 1.8%. The failure bending radius of the micro-thick silicon film attached on a FPCB was 2 mm, and the failure strain was 3.5%, which showed superior flexibility compared with conventional silicon material. Improved flexibility was attributed to a buffering effect of the adhesive between the silicon film and the substrate. The superior flexibility of the thin silicon film demonstrates the possibility for flexible electronic devices with high performance.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.1
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• pp.23-28
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• 2024

Electronic products utilizing flexible devices experience harsh mechanical deformations in real-use environments. As a result, researches on the mechanical reliability of these flexible devices have attracted considerable interest among researchers. This study employed previous bending strain models and finite element analysis to predict the maximum bending strain of metal films deposited on flexible substrates. Bending experiments were simulated using finite element analysis with variations in the material and thickness of the thin films, and the substrate thickness. The results were compared with the strains predicted by existing models. The distribution of strain on the surface of film was observed, and the error rate of the existing model was analyzed during bending. Additionally, a modified model was proposed, providing mathematical constants for each case.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.37-44
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• 2013

It is well known that thermal deformation of electronic packages with Pb-Sn solder and with lead-free solder is significantly affected by material properties consisting the package, as well as those of the solder itself. In this paper, the method for determining coefficient of thermal expansion(CTE) of new material is established by using temperature characteristic of strain gages, and the CTE of molding compound are obtained experimentally. The temperature-dependent CTE of molding compound for Pb-Sn solder and that for lead-free solder are obtained by using strain measurements with well known steel specimen and aluminium specimen as reference specimens, and the CTE's are also measured non-contactly by using moire interferometry. Those results are compared, and the agreement between the two types of strain gage experiment and the moire experiment show the strain gage method used in this paper to be reliable. In the case of the molding compound for Pb-Sn solder, the CTE is measured as approximately $15.8ppm/^{\circ}C$ regardless of the temperature. In the case for the lead-free solder, the CTE is measured as of approximately $9.9ppm/^{\circ}C$ below the temperature of $100^{\circ}C$, and then the CTE is increased sharply depending on the temperature, and reaches to $15.0ppm/^{\circ}C$ at $130^{\circ}C$.

• Transactions of Materials Processing
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• v.29 no.1
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• pp.44-48
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• 2020

Aluminum nitride (AlN), as a substrate material in electronic packaging, has attracted considerable attention over the last few decades because of its excellent properties, which include high thermal conductivity, a coefficient of thermal expansion that matches well with that of silicon, and a moderately low dielectric constant. AlN films with c-axis orientation and thermal conductivity characteristics were deposited by using Pulsed Laser Deposition (PLD). The epitaxial AlN films were grown on sapphire (c-Al₂O₃) single crystals by PLD with AlN target and Y₂O₃ doped AlN target. A comparison of different targets associated with AlN films deposited by PLD was presented with particular emphasis on thermal conductivity properties. The quality of AlN films was found to strongly depend on the growth temperature that was exerted during deposition. AlN thin films deposited using Y₂O₃-AlN targets doped with sintering additives showed relatively higher thermal conductivity than while using pure AlN targets. AlN thin films deposited at 600℃ were confirmed to have highly c-axis orientation and thermal conductivity of 39.413 W/mK.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1231-1236
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• 2004

In the present work, the practical thermal design process of 1 DIN car DVD receiver described. In the course of its efficient design, CAE technique was essentially used. CAE technique has reduced research period, man power and material cost but has increased research convenience, organized results and persuasive power. CAE technique helped to study parameters such as vent, fan and heat sink. Using these elements, it tried to meet optimal thermal solution. But safety standard, printed circuit board and framework mechanism should be considered as the constraint. To overcome these constraints, we tried to communicate and compromise with projectors in charge. After all, the price of those efforts has made the most competitive heat sink for heat dissipation in the 1 DIN car DVD receiver market. Moreover, we are trying to save $3 per product by removing fan. This paper is supposed to show an example of the CAE technique and help thermal designers to make electronic packaging goods.

• Composites Research
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• v.35 no.2
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• pp.69-74
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• 2022

In this study, the conductive paste used in a wide range such as wiring in the electronic packaging field, the automobile industry, and electronic products is manufactured under various process conditions due to the simplicity of the process, and then the thermal, mechanical, and electrical characteristics are analyzed and simulation studies are conducted to optimize the process. to establish the conditions of the conductive paste manufacturing process. First, a conductive paste was prepared by setting various types of binder resin, an essential component of the conductive paste, and characteristics such as thermal conductivity, tensile strength, and elongation were analyzed. Among the binder resins, the conductive paste applied with a flexible epoxy material had the best physical properties, and a simulation study was conducted based on the physical property data base of the conductive face. As a result of the simulation, the best physical properties were exhibited when the Ag flake volume fraction was 60%.