• International Journal of Fuzzy Logic and Intelligent Systems
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• v.16 no.3
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• pp.216-223
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• 2016

This paper proposes a new controller design method for a fork-type lifter (FTL) of a transportation mobile robot. The transportation robot needs to pick up a package from a stack on a storage shelf and move on by a planned path in a logistics center environment. The position of the storage shelf is recognized by reading a QR code on the floor, and using this position, the robot can move to reach the storage shelf and pick up the package. PID controllers and an adaptive controller are designed to control the velocity of two wheels and the position of the FTL. An adaptive controller for the lifter is designed to elevate up and down on a slideway to the correct height position of the package on the stack of the storage shelf. The simulation results show that the PID controllers can respond smoothly to the desired angular velocity and the adaptive controller can adapt quickly and correctly to the desired height.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.45-49
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• 2022

Through Silicon Via (TSV) is a technology that interconnects chips through silicon vias. TSV technology can achieve shorter distance compared to wire bonding technology with excellent electrical characteristics. Due to this characteristic, it is currently being used in many fields that needs faster communication speed such as memory field. However, there is performance degradation issue on TSV technology due to the parasitic capacitance. To deal with this problem, in this study, the parasitic capacitance with TSV design factors is analyzed using commercial tool. TSV design factors were set in three categories: size, aspect ratio, pitch. Each factor was set by dividing the range with TSV used for memory and package. Ansys electronics desktop 2021 R2.2 Q3D was used for the simulation to acquire parasitic capacitance data. DOE analysis was performed based on the reaction surface method. As a result of the simulation, the most affected factors by the parasitic capacitance appeared in the order of size, pitch and aspect ratio. In the case of memory, each element interacted, and in the case of package, it was confirmed that size * pitch and size * aspect ratio interact, but pitch * aspect ratio does not interact.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.425-425
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• 2004

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.149-153
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• 2019

The technology of electronic packaging among semiconductor technologies is evolving as an axis of the market in its own field beyond the simple assembly process of the past. In the field of electronic packaging technology, the packaging of power modules plays an important role for green electric vehicles. In this power module packaging, the thermal reliability is an important factor, and silicon nitride plays an important part of package substrates, Silicon nitride is a compound that is not found in nature and is made by chemical reaction between silicon and nitrogen. In this study, this core material, silicon nitride, was fabricated by reaction bonded silicon nitride. The fabricated silicon nitride was studied for thermo-mechanical properties, and through this, the structure of power module packaging was made using reaction bonded silicon nitride. And the characteristics of stress were evaluated using finite element analysis conditions. Through this, it was confirmed that reaction bonded silicon nitride could replace the silicon nitride as a package substrate.

• Journal of KSNVE
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• v.4 no.3
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• pp.345-352
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• 1994

Electronic products can be subjected to many different forms of shock. These shocks are usually experienced during transporting the electronic products from a manufacturer to customers. Drop tests are performed to test the product fragility before shipment. Package cushioning materials are often used to protect electronic products from severs shock environments. In the present paper, an algorithm to predict the shock responses of the main mechanical parts is developed by use of the shock analysis in which the modal parameters extracted from vibration test are used. These results are in good agreement with the results of drop test. By use of the shock response prediction algorithm developed herein, it is possible to predict the results of drop test at various drop directions and also to select the optimal package cushioning materials.

• Journal of the Korean Society for Library and Information Science
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• v.54 no.4
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• pp.261-281
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• 2020

The importance of long-term preservation of various types of electronic records through dark archives is gradually increasing. However, the current dark archive does not have an optimized information package structure for long-term preservation of electronic records. In order to address these problems, this research proposed four element categories by re-organizing the OAIS reference model information package based on the core process of the dark archiving. The detailed descriptive items of each category consist of a total of 4 upper-level elements and 27 sub elements based on the OAIS reference model, ISO 23081, Records Management Metadata Standard, ISAD(G), ISAAR(CPF), ISDF, and ISDIAH. This structure can be used as a basis for constructing an information package optimized for dark archiving, and is expected to support the long-term preservation of electronic records more efficiently.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.1
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• pp.49-57
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• 2002

Including RF Package inductance, substrate coupling through conductive silicon(Si)-substrate is modeled and quantitatively characterized. 2-port substrate coupling model is extended for the characterization of multi-port substrate coupling between digital circuit block and analog/RF circuit block. Furthermore, scalable parameter extraction model is developed. Multi-port substrate coupling can be investigated by linearly superposing a frequency-dependent 2-port substrate coupling model using scalable parameters. In addition, Substrate coupling including RF package inductance effect is quantitatively investigated. It is shown that package effect increases substrate coupling and shifts a characteristic frequencies(i.e., poles) to the higher frequency range. The proposed methodology can be efficiently used to the mixed-signal circuit performance verification.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

• The Korean Journal of Archival Studies
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• no.16
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• pp.97-146
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• 2007

Those days when people used paper to make up and manage all kinds of documents in the process of their jobs are gone now. Today electronic types of documents have replaced paper. Unlike paper documents, electronic ones contribute to the maximum job efficiency with their convenience in production and storage. But they too have some disadvantages; it's difficult to distinguish originals and copies like paper documents; it's not easy to examine if there is a change or damage to the documents; they are also prone to alteration and damage by the external influences in the electronic environment; and electronic documents require enormous amounts of workforce and costs for immediate measures to be taken according to the changes to the S/W and H/W environment. Despite all those weaknesses, however, electronic documents increasingly account for more percentage in the current job environment thanks to their job convenience and efficiency of production costs. Both the government and private sector have made efforts to come up with plans to maximize their advantages and minimize their risks at the same time. One of the methods is the Authorized Retention Center which is described in the study. There are a couple of prerequisites for its smooth operation; they should guarantee the legal validity of electronic documents in the administrative aspects and first secure the reliability and authenticity of electronic documents in the technological aspects. Responding to those needs, the Ministry of Commerce, Industry and Energy and the Korea Institute for Electronic Commerce, which were the two main bodies to drive the Authorized Retention Center project, revised the Electronic Commerce Act and supplemented the provisions to guarantee the legal validity of electronic documents in 2005 and conducted researches on the ways to preserve electronic documents for a long term and secure their reliability, which had been demanded by the users of the center, in 2006. In an attempt to fulfill those goals of the Authorized Retention Center, this study researched technical standard for electronic record information package of the center and applied the ISO 14721 information package model that's the standard for the long-term preservation of digital data. It also suggested a process to produce and manage information package so that there would be the SIP, AIP and DIP metadata features for the production, preservation, and utilization by users points of electronic documents and they could be implemented according to the center's policies. Based on the previous study, the study introduced the flow charts among the production and progress process, application methods and packages of technical standard for electronic record information package at the center and suggested some issues that should be consistently researched in the field of records management based on the results.

• Journal of the Korean Society for Precision Engineering
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• v.20 no.10
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• pp.183-190
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• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.