• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.159-167
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• 2005

Quantization effects (QEs), which manifests when the device dimensions are comparable to the de Brogile wavelength, are becoming common physical phenomena in the present micro-/nanometer technology era. While most novel devices take advantage of QEs to achieve fast switching speed, miniature size and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. In this paper, an analytical model accounting for the QEs and poly-depletion effects (PDEs) at the silicon (Si)/dielectric interface describing the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of MOS devices with thin oxides is developed. It is also applicable to multi-layer gate-stack structures, since a general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, device characteristics are obtained. Also solutions for C-V can be quickly obtained without computational burden of solving over a physical grid. We conclude with comparison of the results obtained with our model and those obtained by self-consistent solution of the $Schr{\ddot{o}}dinger$ and Poisson equations and simulations reported previously in the literature. A good agreement was observed between them.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1013-1014
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• 2015

Regardless of the strict enforcement of prevention education in accordance with the school facility management standard, safety accidents that lead to human and physical damages occur in current educational facilities because of teenagers with very low sense of responsibility and insensitivity toward fire and facility safety. To ensure educational facility safety, technology that will enable a fast work process and easy confirmation of electronic blueprints and related documents about the educational facility through smart devices at the site by various means is needed. This paper proposes a system design linked to the National Education Information System (NEIS) that uses the document conversion function, high efficiency resolution, and Internet of Things (IoT) to inspect and control the educational facility in the event of a safety accident through the Educational Facility Resource Management System (EFRMS) that manages the electronic blueprints, and various educational facility documents through various smart devices.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1627-1628
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• 2006

In this paper, mesoporous only platinum electrode and micro pore platinum electrode with mesoporous Pt are fabricated and characterized on a silicon substrate to check their usability as enzymeless sensing electrodes for developing non-disposable glucose sensors integrated with silicon CMOS read out circuitry. Since most of electrochemical glucose sensors are disposable due to the use of the enzymes that are living creatures, these are limited to use in the in-vivo and continuous monitoring system applications. The proposed mesoporous Pt electrode with approximately 2.5nm in pore diameter and 150nm in height was fabricated by using a nonionic surfactant $C_{16}EO_8$ and an electroplating technique. The micro pore Pt electrode with mesoporous Pt means the mesoporous Pt electrode fabricated on top of micro pore arrayed Pt electrode with approximately $10{\mu}m$ in pore diameter and $80{\mu}m$ in height. The measured current responses at 10mM glucose solution of plane Pt, micro pore Pt, micro pore with mesoporus Pt, and mesoporous Pt electrodes are approximately $9.9nA/mm^2$, $92.4nA/mm^2$, $3320nA/mm^2$ and $44620nA/mm^2$, respectively. These data indicate that the mesoporous Pt electrode is much more sensitive than the other Pt electrodes. Thus, it is promising for non-disposable glucose sensor and electrochemical sensor applications.

• Journal of the Society of Disaster Information
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• v.14 no.3
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• pp.315-324
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• 2018

Purpose: This paper propose a temporary indoor positioning scheme with devices of internet of things (IoT) for disastrous situations in places without the infrastructure of networks. Method: The proposed scheme is based on the weighted centroid localization scheme that can estimate the position of a target with simple computation. Results: It also is implemented with the IoT devices at the underground parking lot, where the network is not installed, of general office building. According to the experiment results, the positioning error was around 10m without a priori calibration process at $82.5m{\times}56.4m$ underground space. Conclusion: The proposed scheme can be deployed many places without the infrastructure of networks, such as parking lots, warehouses, factory, etc.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.292-295
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• 2004

The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

• Journal of Internet Computing and Services
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• v.20 no.2
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• pp.1-7
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• 2019

The latest mobile applications such as augmented reality, virtual reality, and deep learning can be used efficiently in various fields such as emergency management and game. Accordingly the corresponding applications have been developed for these purposes. However modern mobile applications such as augmented reality and virtual reality increase the energy burden on mobile devices. In order for mobile devices to focus their energy on the latest mobile applications, energy consumption should be minimized for communication and networking, such as cognitive radio. In this paper, we propose a method to reduce the energy consumption of Centralized Cooperative Spectrum Sensing (CCSS) scheme in cognitive radio by devising Stop Reporting Algorithm (SRA). Simulation results show that SRA can reduce energy consumption of mobile devices using cognitive radio.

• Journal of Adhesion and Interface
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• v.23 no.3
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• pp.75-79
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• 2022

Graphene is a two-dimensional carbon allotrope composed of honeycomb sp² hybrid orbital bonds. It shows excellent electrical and mechanical properties and has been spotlighted as a core material for next-generation electronic devices. However, it exhibits low environmental stability due to the easy penetration or adsorption of external impurities from the formation of an unstable interface between the materials in the electronic devices. Therefore, this work aims to improve and investigate the low environmental stability of graphene-based field-effect transistors through direct growth using solid hydrocarbons as a precursor of graphene. Graphene synthesized from direct growth shows high electrical stability through reduction of change in charge mobility and Dirac voltage. Through this, a new approach to utilize graphene as a core material for next-generation electronic devices is presented.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.59-64
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• 2023

In this paper, It is proposed through the empirical design of a Conducted EMI filter for noise reduction of power used in electronic devices. For the proposed structure, A-type, B-type, C-type, and D-type structures were designed, and conductive noise reduction was confirmed by using an LC network with various X-capacitors, Y-capacitors, and Air-inductors. 10 [μH] was used for L1 and L2, and 4.7 [nF] was used for C1 and C2. L3 for common mode used 13[μH], and C5, C6, C7 were designed using 10[nF]. The measured insertion loss values of the designed EMI filter were -74.4[dB] at 3.2MHz, -75.4[dB] at 4MHz, and -75.3[dB] at 13.56MHz. Therefore, the proposed EMI filter will be able to reduce power supply noise used in various electronic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.133-133
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• 2008

Recently, as the down-scailing of field-effect transistor devices continues, Schottky-barrier field-effect transistors (SB-FETs) have attracted much attention as an alternative to conventional MOSFETs. SB-FETs have advantages over conventional devices, such as low parasitic source/drain resistance due to their metallic characteristics, low temperature processing for source/drain formation and physical scalability to the sub-10nm regime. The good scalability of SB-FETs is due to their metallic characteristics of source/drain, which leads to the low resistance and the atomically abrupt junctions at metal (silicide)-silicon interface. Nevertheless, some reports show that SB-FETs suffer from short channel effect (SCE) that would cause severe problems in the sub 20nm regime.[Ouyang et al. IEEE Trans. Electron Devices 53, 8, 1732 (2007)] Because source/drain barriers induce a depletion region, it is possible that the barriers are overlapped in short channel SB-FETs. In order to analyze the SCE of SB-FETs, we carried out systematic studies on the Schottky barrier overlapping in short channel SB-FETs using a SILVACO ATLAS numerical simulator. We have investigated the variation of surface channel band profiles depending on the doping, barrier height and the effective channel length using 2D simulation. Because the source/drain depletion regions start to be overlapped each other in the condition of the $L_{ch}$~80nm with $N_D{\sim}1\times10^{18}cm^{-3}$ and $\phi_{Bn}$ $\approx$ 0.6eV, the band profile varies as the decrease of effective channel length $L_{ch}$. With the $L_{ch}$~80nm as a starting point, the built-in potential of source/drain schottky contacts gradually decreases as the decrease of $L_{ch}$, then the conduction and valence band edges are consequently flattened at $L_{ch}$~5nm. These results may allow us to understand the performance related interdependent parameters in nanoscale SB-FETs such as channel length, the barrier height and channel doping.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1016-1018
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• 1995

In this paper, we studied the electrical and the microwave properties of the amorphous $As_{10}Ge_{15}Te_{75}$ thin film. The electrical properties of a-$As_{10}Ge_{15}Te_{75}$ thin film were examined d.c. and a.c. bias with annealing condition. As the result of the electrical properties, we observed the physical characteristics of a-$As_{10}Ge_{15}Te_{75}$ thin film such as the density of defect states, characteristic relaxation time, localized density of states, and localized wave function by using CBH and QMT model. We also examined the microwave conduction properties before and after d.e. switching.