• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5614-5633
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• 2018

Mobile Edge Computing (MEC) and Wireless Power Transfer (WPT) are both recognized as promising techniques, one is for solving the resource insufficient of mobile devices and the other is for powering the mobile device. Naturally, by integrating the two techniques, task will be capable of being executed by the harvested energy which makes it possible that less intrinsic energy consumption for task execution. However, this innovative integration is facing several challenges inevitably. In this paper, we aim at prolonging the battery life of mobile device for which we need to maximize the harvested energy and minimize the consumed energy simultaneously, which is formulated as residual energy maximization (REM) problem where the offloading ratio, energy harvesting time, CPU frequency and transmission power of mobile device are all considered as key factors. To this end, we jointly optimize the offloading ratio, energy harvesting time, CPU frequency and transmission power of mobile device to solve the REM problem. Furthermore, we propose an efficient convex optimization and sequential unconstrained minimization technique based combining method to solve the formulated multi-constrained nonlinear optimization problem. The result shows that our joint optimization outperforms the single optimization on REM problem. Besides, the proposed algorithm is more efficiency.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.9-15
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• 2018

This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.603-606
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• 2019

In this paper, we propose a slotted-ALOHA-based random access protocol and derive the optimal number of random slots that maximize channel throughput when multiple energy harvesting sensor devices perform random access in wireless-powered sensor networks (WPSN). Throughput numerical analysis, we prove that the throughput has a concavity with respect to the number of random slots and obtain the optimal number of slots. Simulation results show that the throughput of the proposed slotted ALOHA-based random access protocol is maximize when the derived optimal number of slots is employed in the considered WPSN.

• Nuclear Engineering and Technology
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• v.50 no.8
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• pp.1298-1305
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• 2018

The use of System-on-Chip (SoC) solutions in the design of on-board data handling systems is an important step towards further miniaturization in space. However, the Total Ionizing Dose (TID) and Single Event Effects (SEE) characterization of these complex devices present new challenges that are either not fully addressed by current testing guidelines or may result in expensive, cumbersome test configurations. In this paper we report the test setups, procedures and results for TID testing of a SoC microcontroller both using standard $^{60}Co$ and low-energy protons beams. This paper specifically points out the differences in the test methodology and in the challenges between TID testing with proton beam and with the conventional gamma ray irradiation. New test setup and procedures are proposed which are capable of emulating typical mission conditions (clock, bias, software, reprogramming, etc.) while keeping the test setup as simple as possible at the same time.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.201-206
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• 2019

This study presents the design and experimental result of a GaN-based DC-DC converter with an integrated gate driver. The GaN device is attractive to power electronic applications due to its superior device performance. However, the switching loss of a GaN-based power converter is susceptible to the common source inductance, and converter efficiency is severely degraded with a large loop inductance. The objective of this study is to achieve high-efficiency power conversion and the highest power density using a multiphase integrated half-bridge GaN solution with minimized loop inductance. Before designing the converter, several GaN and Si devices were compared and loss analysis was conducted. Moreover, the impact of common source inductance from layout parasitic inductance was carefully investigated. Experimental test was conducted in buck mode operation at 48 -12 V, and results showed a peak efficiency of 97.8%.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Korean Journal of Materials Research
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• v.31 no.8
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• pp.471-479
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• 2021

The electrochemical reaction between lead borate glass frit doped with Sn metal filler and Ni-Cr wire of a J-type resistor during a term of Joule heating is investigated. The fusing behavior in which the Ni-Cr wire is melted is not observed for the control group but measured for the Sn-doped specimen under 30 V and 500 mA. The Sn-doped lead borate glass frit shows a fusing property compared with other metal-doped specimens. Meanwhile, the redox reaction significantly contributes to the fusing behavior due to the release of free electrons of the metal toward the glass. The electrons derived from the glass, which used Joule heat to reach the melting point of Ni-Cr wire, increase with increasing corrosion rate at interface of metal/glass. Finally, the confidence interval is 95 ± 1.95₉ %, and the adjusted regression coefficient, R in the optimal linear graph, is 0.93, reflecting 93% of the data and providing great potential for fusible resistor applications.

• Journal of Auto-vehicle Safety Association
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• v.11 no.2
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• pp.11-16
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• 2019

This paper suggests an algorithm for detecting fault of longitudinal controller in autonomous vehicles. Guaranteeing safety in fault situation is essential because electronic devices in vehicle are dependent each other. Several methods like alarm to driver, ceding control to driver, and emergency stop are considered to cope with fault. This research investigates the fault monitoring process in fail-safe system, for controller which is responsible for accelerating and decelerating control in vehicle. Residual is computed using desired acceleration control command and actual acceleration, and detection of its abnormal increase leads to the decision that system has fault. Before computing residual for controller, health monitoring process of acceleration signal is performed using hardware and analytic redundancy. In fault monitoring process for controller, a process model which is fitted using driving data is considered to improve the performance. This algorithm is simulated via MATLAB tool to verify performance.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.3
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• pp.205-213
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• 2021

Due to the advantage of reducing the voltage applied to the switch semiconductor, the input series and output parallel combination is widely used in systems with high input voltage and large output current. On the other hand, the LLC converter is widely used as a high-efficiency power converter, and when connected by ISOP combination, there is a possibility that input voltage imbalance may occur due to a mismatch of passive devices. To avoid damaging the switching device, this study analyzed the DC-link voltage imbalance of a high-capacity supply using an ISOP LLC converter. In addition, the case where DC-link unbalance control was applied and the case not applied was analyzed respectively. Based on this analysis, an initial start-up algorithm was proposed to prevent input power semiconductor device damage due to DC-link over-voltage. The effectiveness of the proposed algorithm has been verified through simulations and experiments.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.1-12
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• 2021

3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.