• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.1
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• pp.90-97
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• 2019

The charge redistribution digital-to-analog converter(CR-DAC) is often used for successive approximation register analog-to-digital converter(SAR ADC) that requiring low power consumption and small circuit area. However, CR-DAC is required 2 to the power of N unit capacitors to generate reference voltage for successive approximation of the N-bit SAR ADC, and many unit capacitors occupy large circuit area and consume more power. In order to improve this problem, this paper proposes SAR ADC using series capacitor DAC. The series capacitor DAC is required 2(1+N) unit capacitors to generate reference voltage for successive approximation and charges only two capacitors of the reference generation block. Because of these structural characteristics, the SAR ADC using series capacitor DAC can reduce the power consumption and circuit area. Proposed SAR ADC was designed in CMOS 180nm process, and at 1.8V supply voltage and 500kS/s sampling rate, proposed 6-bit SAR ADC have signal-to-noise and distortion ratio(SNDR) of 36.49dB, effective number of bits(ENOB) of 5.77-bit, power consumption of 294uW.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.971-976
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• 2014

In this paper, we proposed a low power algorithm using state transition ready method. The proposed algorithm defined a sleep state, a idle state and a run state for the task. A state transition occurring at the time due to the delay time created in order to reduce the power consumption state in the middle of each inserted into the ready state. The ready state considering a power consumption and a delay time in state transition. A scheduling step of performing the steps in excess of the increasing problems have the delay time is long. The power consumption increased for the operation step increase. A state transition from a sleep state with the longest delay time in operating state occurs when the state is switched by the time delay caused by the increase in operating time reduces the overall power consumption reduced. Experiments [6] were compared with the results of the power consumption. The experimental results [6] is reduced power consumption than the efficiency of the algorithm has been demonstrated.

• ETRI Journal
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• v.30 no.6
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• pp.799-806
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• 2008

In this paper, a new design for an error correcting code (ECC) is proposed. The design is aimed to build an ECC circuitry with minimal power consumption. The genetic algorithm equipped with the symbiotic mechanism is used to design a power-efficient ECC which provides single-error correction and double-error detection (SEC-DED). We formulate the selection of the parity check matrix into a collection of individual and specialized optimization problems and propose a symbiotic evolution method to search for an ECC with minimal power consumption. Finally, we conduct simulations to demonstrate the effectiveness of the proposed method.

• The Journal of the Korea institute of electronic communication sciences
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• v.2 no.3
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• pp.163-167
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• 2007

In this paper, to design 8 bit RISC Microprocessor, a method of Clock Gating to reduce electric power consumption is proposed. In order to examine the priority, the comparison results of between a 8 bit Microprocessor which is not considered Low Power consumption and which is considered Low Power consumption using a methods of Clock Gating are represented. Within the a few periods, the results of comparing with a Microprocessor not considered the utilization of Clock Gating shows that the reduction of dynamic dissipation is minimized up to 21.56%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.207-211
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• 2004

We have performed computer simulation to obtain a globa1 optimization of power consumption and viewing angle characteristic of reflective twisted nematic (R-TN) mode liquid crystal display (LCD) with sin81e polarizer and λ/4 plate. Our studies shout that with increasing the twist angle, a steepness of reflectance-voltage curve increase, operation voltages decreases, the region where contrast ratio (CR) greater than 10 increases but the reflectance of the white state starts to decrease at above the twist angle of 75$^{\circ}$. Above the twist angle of 90$^{\circ}$, the R-TN mode LCD shows the most favorable combination of low consumption and good viewing angle characteristic.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.11-17
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• 2012

The VLC system undertakes both missions of illumination and wireless communication. It is difficult to design a VLC system with optimal performance due to the trade-offs between power consumption and channel quality. In this paper, the VLC system design problem is solved by using multi-objective optimization method. For optimization, the multi-objective function is formulated with respect to power consumption, received power, and SNR under the constraints on the system variables. Through the multi-objective optimization, it is possible to obtain the solutions that satisfies both minimum power consumption and maximum channel quality.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.2
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• pp.164-170
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• 2004

Recently, the demand for micro hard disk drive that provides high-capacity removable storage for handhold electronic devices is growing very rapidly Reducing power consumption is one of the primary control objectives in micro disk drives. The input power delivered to the seek servo system is consumed as heat by the transistors of power amplifier and motor coil resistance. In this paper, we present a new seek servo controller for minimizing the power consumption. We use a Fourier decomposition and nonlinear programming to determine the optimum seek profile that minimizes the power consumption. Also, the trajectory tracking controller is developed for exact tracking of the optimum seek profile. Finally, we present some experimental results using a commercially available micro disk drive in order to demonstrate the superior performance of the proposed controller.

• ETRI Journal
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• v.26 no.6
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.5
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• pp.215-225
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• 2020

Light detection and ranging (LiDAR) sensors detect the distance of the surrounding environment and objects. Conventional LiDAR sensors require a certain amount of a power because they detect objects by transmitting lasers at a regular interval depending on a constant resolution. The constant power consumption from operating multiple LiDAR sensors is detrimental to autonomous and electric vehicles using battery power. In this paper, we propose two algorithms that improve the inefficient power consumption during the constant operation of LiDAR sensors. LiDAR sensors with algorithms efficiently reduce the power consumption in two ways: (a) controlling the resolution to vary the laser transmission period (T_P) of a laser diode (LD) depending on the vehicle's speed and (b) reducing the static power consumption using a sleep mode depending on the surrounding environment. A proposed LiDAR sensor with a resolution control algorithm reduces the power consumption of the LD by 6.92% to 32.43% depending on the vehicle's speed, compared to the maximum number of laser transmissions (N_x·max). The sleep mode with a surrounding environment-sensing algorithm reduces the power consumption by 61.09%. The proposed LiDAR sensor has a risk factor for 4-cycles that does not detect objects in the sleep mode, but we consider it to be negligible because it immediately switches to an active mode when a change in surrounding conditions occurs. The proposed LiDAR sensor was tested on a commercial processor chip with the algorithm controlling the resolution according to the vehicle's speed and the surrounding environment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1702-1708
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• 2013

OLED has good efficiency of power consumption by having no power consumption from black color as different with LCD. when it has white color, all RGB pixel should be glowing with high power consumption and that can make it has short life time. This paper suggest the way of low power consumption for OLED panel using adaptive luminance enhancement with color compensation and implement it as hardware. This way which is based on luminance information of input image makes converted luminance value from each pixel in real time. There is with using the basic idea of chromaticity reduction algorithm, showing new algorithm of color correction. And performance of proposed method was confirmed by comparing the conventional method in experiments about 48.43% current reduction. The proposed method was designed by Verilog HDL and was verified by using OpenCV and Windows Program.