• 마이크로전자및패키징학회지
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• 제18권2호
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• 대한금속재료학회지
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• 제48권6호
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• pp.557-564
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• 2010

Formation of Sn through-silicon-via (TSV) and its interconnection processes were studied in order to form a three-dimensional interconnection structure of chip-stack packages. Different from the conventional formation of Cu TSVs, which require a complicated Cu electroplating process, Sn TSVs can be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing a much wider process window for the formation of Sn TSVs compared to the conventional Cu TSV process. Interlocking joints were processed by intercalation of Cu bumps into Sn vias to form interconnections between chips with Sn TSVs, and the mechanical integrity of the interlocking joints was evaluated with a die shear test.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1673-1678
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• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• Journal of Mechanical Science and Technology
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• 제14권2호
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• pp.251-258
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• 2000

Thermal deformation in an electronic package due to thermal strain mismatch is investigated. The warpage and the in-plane deformation of the package after encapsulation is analyzed using the laminated plate theory. An exact solution for the thermal deformation of an electronic package with circular shape is derived. Theoretical results are presented on the effects of the layer geometries and material properties on the thermal deformation. Several applications of the exact solution to electronic packaging product development are illustrated. The applications include lead on chip package, encapsulated chip on board and chip on substrate.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.49-54
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• 1993

This paper discusses the reliability of solder joints of electronic devices on printed circuit board. Solder application is usually done by screen printing method for the bonding between outer leads of devices and thick film(Ag/Pd) pattern on Hybrid IC as wel1 as Cu lands on PCB. As result of thermal stresses generated at the solder joints due to the differences of thermal expansion coefficients between packge body and PCB, Micro cracking often occurs due to thermal fatigue failure at solder joints. The initiation and the propagate of solder joint crack depends on the environmental conditions, such as storage temperature and thermal cycling. The principal mechanisms of the cracking pheno- mana are the formation of kirkendal void caused by the differences in diffusion rate of materials, ant the thermal fatigue effect due to the differences of thermal expansion coefficient between package body and PCB. Finally, This paper experimentally shows a way to supress solder joints cracks by using low-${\alpha}$ PCB and the packages with thin lead frame, and investigates the phenomena of diffusion near the bonding interfaces.

• 한국정밀공학회지
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• 제21권2호
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• pp.138-144
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• 2004

The initiation and the propagation of solder joint crack depend on its environmental conditions, such as high temperature creep and thermal fatigue. Creep is known to be the most important factor for the mechanical failure of solder joints in micro-electronic components and micro-systems. This is mainly caused by the different thermal expansion coefficients of the materials used in the micro-electronic packages. To determine the reliability of solder joints and consequently the electronic components, the characterization of the creep behavior of this group of materials is crucial. This paper is to apply the theory of creep into solder joints and to provide related technical information needed for evaluation of reliability of solder joint to failure. 63Sn-37Pb solder was used in this study. This paper experimentally shows a way to enhance the reliability of solder joints.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.275-278
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• 2002

Conductive adhesives are commonly used for the interconnections of fine pitch, small packages like mobile applications. Since conductive particles connect mechanically with contact pads to give somewhat higher contact resistance, a metallurgical interconnection, which provides both fine pitch and low resistance, was studied using silver ball and indium which can be made at low temperatures. The connection resistance of the In-Ag metallurgical interconnection was lower than that of the Ni/Au-Ag mechanical interconnection and the former showed little dependency on the bonding load in contrast to the latter.

• 정보관리연구
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• 제41권4호
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• pp.69-91
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• 2010

제한된 예산, 고가의 패키지 구독비, 출판사 주도의 라이선스 협상 등의 불리한 환경에서 자관의 실정에 맞는 전자저널을 구성하기 위해 도서관은 전자저널 이용데이터를 수집하고 분석해야 한다. 본 연구는 전자저널 이용통계 연구 동향 및 COUNTER 3판에 근거한 이용통계 제공 현황을 살펴보고 현장에서 쉽게 활용 가능한 이용통계 분석의 가이드라인을 제시하고자 하였다. 현재 제공되는 이용통계 보고서를 기반으로 분석할 수 있는 핵심 이용통계치로 저널별 원문이용도, 저널이용률, 원문이용단가, 고이용군, 저이용군을 제안함으로써 전자저널 관리를 위한 이용통계의 효과적인 활용 방안을 다루었다.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.441-446
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• 2011

Radio frequency identification (RFID) tags are cheap and simple devices that can store unique identification information and perform simple computation to keep better inventory of packages. Security protocol for RFID tags is needed to ensure privacy and authentication between each tag and their reader. In order to accomplish this, in this paper, we analyzed a lightweight privacy and authentication protocol for passive RFID tags.