• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.57-65
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• 2001

Economical consumption of energy, longer life of lamps, higher lighting comfort and new aesthetic of illumination is subject of numerous research and development works. The halogen lamps are an example of positive solution some of above mentioned problems. The electronic transformers are more frequent used for their supply. In comparison with conventional transformers they have less weight, less volume and 60% less power tosses. Their advantages are particular visible, when the hybrid technique is applied. The paper presents the results of engineering research and development works carried out ill Private Institute of Electronic Engineering, in R. & D. Center for Hybrid Microelectronics and Resistors and in Technical School of Communications in Krakow, in the field of the design and exploitation tests of hybrid converters 220V AC /12V DC (electronic transformers) and electronic ballasts destined for the supply of halogen lamps 20W to 150W and fluorescent lamps respectively. To perform the converters, thick film technology and surface mount technology were used. For the protection of converter electronic circuit the thick film temperature sensor and transistors were applied. Moreover the paper presents the base application circuits of elaborated converters, their technical parameters and exploitation results. The development perspectives of hybrid domain of hybrid circuits are also discussed.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.43-48
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• 2001

Economical consumption of energy, longer life of lamps, higher lighting comfort and new aesthetic of illumination is subject of numerous research and development works. The halogen lamps are an example of positive solution some of above mentioned problems. The electronic transformers are more frequent used for their supply. In comparison with conventional transformers they have less weight, less volume and 60% less power losses. Their advantages are particular visible, when the hybrid technique is applied. The paper presents the results of engineering research and development works carried out in Private Institute of Electronic Engineering, in R. & D. Center for Hybrid Microelectronics and Resistors and in Technical School of Communications in Krakow, in the field of the design and exploitation tests of hybrid converters 220V AC /12V DC (electronic transformers) and electronic ballasts destined for the supply of halogen lamps 20W to 150W and fluorescent lamps respectively. To perform the converters, thick film technology and surface mount technology were used. For the protection of converter electronic circuit the thick film temperature sensor and transistors were applied. Moreover the paper presents the base application circuits of elaborated converters, their technical parameters and exploitation results. The development perspectives of such domain of hybrid circuits are also discussed.

• 컴퓨터교육학회논문지
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• 제10권5호
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• pp.53-60
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• 2007

학습효율의 향상을 위해 본 논문에서는 웹기반 가상실험시스템과 원격실험시스템을 적절하게 통합하여 전기전자회로에 대한 하이브리드 실험시스템을 구현하였다. 먼저, 전기/전자회로 실험에 대한 웹기반 가상실험실을 개발하여 개념학습, 가상실험, 평가등의 3개의 주요 세션과 그에 대한 관리시스템으로 구성하였다. 다음으로 가상실험을 진행하는 동안 발생할 수 있는 현실감의 부족성 문제를 해결하기 위해 전기전자회로에 대한 원격실험시스템을 구현하였다. 제안된 가상/원격실험시스템은 독립적인 형태로 사용될 수도 있지만, 학습효율을 극대화하기 위해서 두 개의 시스템을 통합하여 하이브리드 전기전자 실험시스템을 구현하였다.

• E2M - 전기 전자와 첨단 소재
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• 제11권11호
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• pp.53-65
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• 1998

Planar lightwave circuits (PLCs) provide various important devices for optical wavelength division multiplexing (WDM) systems, subscriber networks and etc. This paper reviews the recent progress and future prospects of PLC technologies including arrayed-waveguide grating multiplexers, optical add/drop multiplexers, programmable dispersion equalizers and hybrid optoelectronics integration technologies.

• 조명전기설비학회논문지
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• 제29권3호
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• pp.81-87
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• 2015

In order to effectively protect electrical and electronic circuits which are extremely susceptible to lightning surges, multi-stage surge protection circuits are required. This paper presents the operational characteristics of the two-stage hybrid surge protection circuit in extra-low voltage DC power lines. The hybrid surge protective device consists of the gas discharge tube, transient voltage suppressor, and series inductor. The response characteristics of the proposed hybrid surge protective device to combination waves were investigated. As a result, the proposed two-stage surge protective device to combination wave provides the tight clamping level of less than 50V. The firing of the gas discharge tube to lightning surges depends on the de-coupling inductance and the rate-of-change of the current flowing through the transient voltage suppressor. The coordination between the upstream and downstream components of the hybrid surge protective device was satisfactorily achieved. The inductance of a de-coupler in surge protective circuits for low-voltage DC power lines, relative to a resistance, is sufficiently effective. The voltage drop and power loss due to the proposed surge protective device are ignored during normal operation of the systems.

• 마이크로전자및패키징학회지
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• 제4권2호
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• pp.1-16
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• 1997

Modern electronic components require its sophistication to meet the stringent requirements which are demanded for high tech industry. In an attempt to meet to such demand miniaturization of the components has been considrably progressed to increase its circuit density. High density of the components can be achieved by an innovative technology of design and manufacturing with functionally improved or new materials such as small bulk devices thick films and thin films circuits (2D). Recently many efforts have been extensively made in the community of the Hybrid Microelectronics through out world. In this paper an approach is introduced in realizing a sophisticated passive circuit for the microelectronics applications by use of hybrid thick/thin films technology. The merit of this technology is discussed and the future trend is speculated.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.391-397
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• 2006

We present investigations of a hybrid type superconducting fault current limiter (SFCL), which consists of transformers and resistive superconducting elements. The secondary windings of the transformer were separated into several electrically isolated circuits and linked inductively with each other by mutual flux, each of which has a superconducting current limiting element of $YBa_2Cu_3O_7$ (YBCO) stripes as a current limiting element. Simple connection in series of the SFCL elements tends to produce ill-timed quenching because of power dissipation unbalance between SFCL elements. Both electrical isolation and mutual flux linkage of the elements provides a solution to power dissipation unbalance, inducing simultaneous quench and current redistribution of the YBCO films. This design enables to increase the voltage rating of SFCL with given YBCO stripes.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.