• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.1
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• pp.24-28
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• 2012

In this study, we fabricated an amorphous InGaZnO pseudo-MOS transistor (a-IGZO ${\Psi}$-MOSFET) with a stacked $Si_3N_4/SiO_2$ (NO) gate dielectric and evaluated reliability of the devices with various thicknesses of a $SiO_2$ buffer layer. The roles of a $SiO_2$ buffer layer are improving the interface states and preventing degradation caused by the injection of photo-created holes because of a small valance band offset of amorphous IGZO and $Si_3N_4$. Meanwhile, excellent electrical properties were obtained for a device with 10-nm-thick $SiO_2$ buffer layer of a NO stacked dielectric. The threshold voltage shift of a device, however, was drastically increased because of its thin $SiO_2$ buffer layer which highlighted bias and light-induced hole trapping into the $Si_3N_4$ layer. As a results, the pseudo-MOS transistor with a 20-nm-thick $SiO_2$ buffer layer exhibited improved electrical characteristics and device reliability; field effective mobility(${\mu}_{FE}$) of 12.3 $cm^2/V{\cdot}s$, subthreshold slope (SS) of 148 mV/dec, trap density ($N_t$) of $4.52{\times}1011\;cm^{-2}$, negative bias illumination stress (NBIS) ${\Delta}V_{th}$ of 1.23 V, and negative bias temperature illumination stress (NBTIS) ${\Delta}V_{th}$ of 2.06 V.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.63-69
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• 2019

Soldering technology has been used in electronic industry for a long time. However, due to solder fatigue characteristics, automotive electronics are searching the semi-permanent interconnection technology such as press-fit method. Press fit interconnection is a joining technology that mechanically inserts a press fit metal terminal into a through hole in a board, and induces a strong bonding by closely contacting the inner surface joining of the through hole by plastic deformation of press-fit terminal. In this paper, the bonding properties of press-fit interconnection are investigated with PCB hole size and surface finishes. In order to compare interconnection reliability between the press fit and soldering, the change in resistance of the press-fit and soldering joints was observed during thermal shock test. After thermal cycling, the failure modes are investigated to reveal the degradation mechanism both press-fit and soldering technology.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.1
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• pp.82-89
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• 2017

In this work, InGaZnO thin film transistors with Ni, Al and ITO source and drain electrode materials were fabricated to analyze a hot carrier induced device degradation according to the electrode materials. From the electrical measurement results with electrode materials, Ni device shows the best electrical performances in terms of mobility, subthreshold swing, and $I_{ON}/I_{OFF}$. From the measurement results on the device degradation with source and drain electrode materials, Al device shows the worst device degradation. The threshold voltage shifts with different channel widths and stress drain voltages were measured to analyze a hot carrier induced device degradation mechanism. Hot carrier induced device degradation became more significant with increase of channel widths and stress drain voltages. From the results, we found that a hot carrier induced device degradation in InGaZnO thin film transistors was occurred with a combination of large channel electric field and Joule heating effects.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.44 no.1
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• pp.51-59
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• 2021

Electronic document communication based on a digital channel is becoming increasingly important with the advent of the paperless age. The electronic document based on PDF format does not provide a powerful customer experience for a mobile device user despite replacing a paper document by providing the content integrity and the independence of various devices and software. On the other hand, the electronic document based on HTML5 format has weakness in the content integrity as there is no HTML5 specification for the content integrity despite its enhanced customer experience such as a responsive web technology for a mobile device user. In this paper, we design the Document-HTML, which provides the content integrity and the powerful customer experience by declaring the HTML5 constraint rules and the extended tags to contain the digital signature based on PKI. We analyze the existing electronic document that has been used in the major financial enterprise to develop a sample. We also verify the Document-HTML by experimenting with the sample of HTML electronic communication documents and analyze the PKI equation. The Document-HTML document can be used as an authorized electronic document communication and provide a powerful customer experience in the mobile environment between an enterprise and a user in the future.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.436-439
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• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.36-40
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• 2007

Inorganic layers, such as SiOxNy and SiOx deposited using plasma sublimation method, were tested as passivation layer for organic thin-film-transistors (OTFTs). OTFTs with bottom-gate and bottom-contact structure were fabricated using pentacene as organic semiconductor and an organic gate insulator. SiOxNy layer gave little change in characteristics of OTFTs, but SiOx layer degraded the performance of OTFTs severely. Inferior barrier properties related to its lower film density, higher water vapor transmission rate (WVTR) and damage due to process environment of oxygen of SiOx film could explain these results. Polyurea and polyvinyl acetates (PVA) were tested as organic passivation layers also. PVA showed good properties as a buffer layer to reduce the damage come from the vacuum deposition process of upper passivation layers. From these results, a multilayer structure with upper SiOxNy film and lower PVA film is expected to be a superior passivation layer for OTFTs.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.16 no.3
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• pp.138-145
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• 2017

With the increasing use of smart electronic devices, the size of the related I/O interface market is increasing rapidly. Demand is also growing for the continuous increase of data and video signals-such as faster data processing speed and data storage capacity-in the smart electronic device input/output interface market. Currently, the POF hybrid cable used in the smart electronic device input / output interface market cannot transmit over a long distance because the optical loss is too large, and the GOF hybrid cable is both vulnerable to bending and other sudden outside changes, and expensive. Therefore, in this study, the design and fabrication of a GOF hybrid cable and fiber guide were carried out in order to develop a cable which can easily withstand external impact, has low optical losses, and meets the demand for continuous data and video signal increase in the smart electronic device input / output interface market.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.120-131
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• 2007

A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.5
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• pp.381-388
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• 2003

In this paper, the IED(Intelligent Electronic Devices) with the consideration of harmonic problems is discussed, With significant development of power electronics technology, the proliferation of a nonlinear load has more deteriorated power quality, As continuous harmonic current makes for a shortening lifetime, overheat and abnormal operation, it should be considered to improve these problems. However, the conventional digital protective relay which eliminates harmonic elements with orthogonal filter has a defect on actually implementation. The prototype IED is constructed with Digital Signal Processor(TMS320C32) and Complex Programmable Logic Device. According to the experiment and simulation results, it is proved that the proposed system has good performance of measuring harmonic factors and protecting electrical equipment.