• Title/Summary/Keyword: Electronic Circuits

Search Result 962, Processing Time 0.031 seconds

A Design of Novel Class-A bipolar $CCII{\pm}$ and Its Application to output Current Controllable CCII+ (새로운 A급 바이폴라 $CCII{\pm}$와 이를 이용한 출력 전류 제어 가능한 CCII+ 설계)

  • Cha, Hyeong-Woo
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.48 no.11
    • /
    • pp.48-56
    • /
    • 2011
  • Novel class-A bipolar current conveyor($CCII{\pm}$) with differential current output and its application to output current controllable CCII+ for electronic tuning systems are designed. The $CCII{\pm}$ is consists of conventional CCII+ and complementary cross current sources. The CCII+ with controllable the output current consists of the $CCII{\pm}$ and a current gain amplifier with single-ended current output. The simulation result shows that the $CCII{\pm}$ has current input impedance of $1.9{\Omega}$ and a good linearity for voltage and current follower. The proposed CCII+ has 3-dB cutoff frequency of 10MHz for the range over bias control current $100{\mu}A$ to 10mA. The range of output current control is four decade. The power dissipation of the CCII+ is 4.5mW at supply voltage of ${\pm}2.5V$.

A Study on Requirements Analysis for Obtaining Intrinsic Safety Certification (본질안전인증 취득을 위한 요구조건 분석에 관한 연구)

  • Oh, Kyutae
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.54 no.1
    • /
    • pp.147-151
    • /
    • 2017
  • Areas of concentrations that can be exploited at all times, such as gas reservoirs in crude oil tanks, are called zero zones. In order to use various equipment in Zone 0, an intrinsically safe certification must be obtained that can guarantee that sparks will not occur in nature. Most devices that acquire intrinsic safety certification are mostly simple single-component devices or devices. In this study, it was a very difficult process because we intend to acquire the intrinsic safety certification of an electronic circuit including an ultrasonic generator and a microcontroller in which hundreds of components are mounted on a PCB substrate. Through this study, we have been able to understand how to design a circuit for intricate intrinsic safety certification. and Using the results of this study, it will be easier to design intrinsically safe circuits when trying to develop a circuit that can obtain intrinsic safety certification.

Core Circuit Technologies for PN-Diode-Cell PRAM

  • Kang, Hee-Bok;Hong, Suk-Kyoung;Hong, Sung-Joo;Sung, Man-Young;Choi, Bok-Gil;Chung, Jin-Yong
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.8 no.2
    • /
    • pp.128-133
    • /
    • 2008
  • Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

A 900 MHz Zero-IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

  • Kim, Changwan;Lee, Seungsik;Choi, Sangsung
    • ETRI Journal
    • /
    • v.36 no.3
    • /
    • pp.352-360
    • /
    • 2014
  • This paper presents a 900 MHz zero-IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ${\Delta}{\Sigma}$ fractional-N frequency synthesizer. In the RF front end, re-use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current-driven passive mixer in Rx and voltage-mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty-cycle in local oscillator clocks. The overall Rx-baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a $0.18{\mu}$ CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of -2 dBm, a sensitivity level of -103 dBm at 100 Kbps with PER < 1%, an Rx input $P_{1dB}$ of -11 dBm, and an Rx input IP3 of -2.3 dBm.

Development of an Electronic Starting Controller for Starting Motor of Packaged Power Systems (이동식발전설비의 기동전동기용 전자식 시동 제어장치 개발)

  • Kim, Jong-Su;Yoon, Kyoung-Kuk;Seo, Dong-Hoan
    • Journal of Advanced Marine Engineering and Technology
    • /
    • v.36 no.5
    • /
    • pp.700-706
    • /
    • 2012
  • The core technology of a starting device in the packaged power system is the pinion gear shifting device and to limit the initial starting voltage. Although the conventional products have been used the starting controller using mechanical contactor, these have a big problem such as the uncertainty for the start of starting motor after a pinion gear is completely shifted or the arc demage due to high current. In this study, in order to solve these problems, we designed and fabricated a new product to achieve the safety and reliability as follows: the pinion gear-shifting control circuits to eliminate the uncertainty of the start, the starting control system using semiconductor device to prevent the arc demage of contactor caused by high current, a start safety devices for soft starting of series motor. In addition, we obtained the electrical safety by separating the pinion gear control circuit and the source circuit of motor.

Implementation of Capacitance Measurement Equipment for Fault Diagnosis of Multi-channel Ultrasonic Probe (다중채널 초음파 프로브 고장진단을 위한 커패시턴스 측정 장치 구현)

  • Kang, Bub-Joo;Kim, Yang-soo
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.20 no.1
    • /
    • pp.175-184
    • /
    • 2016
  • In this paper, we propose the method to measure the capacitances using not LCR meter but capacitance to voltage(C/V) conversion. And we design the analog MUX circuits that convert 192 channels to 6 MUX channels in order to implement the diagnosis of multi-channel ultrasonic probe. This paper derives the conversion function that converts the digital voltage of each MUX channel to the capacitance using the least squares method because the circuit characteristics that convert the voltage of each MUX channel to the capacitance are different. The developed prototype illustrates the performance test results that the measure times are measured by within 4sec and the measure error rates of maximum, minimum, and average values are within 5% in terms of the repeated measurements of all 192 channels.

Effects of Simultaneous Bending and Heating on Characteristics of Flexible Organic Thin Film Transistors

  • Cho, S.W.;Kim, D.I.;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2013.02a
    • /
    • pp.470-470
    • /
    • 2013
  • Recently, active materials such as amorphous silicon (a-Si), poly crystalline silicon (poly-Si), transition metal oxide semiconductors (TMO), and organic semiconductors have been demonstrated for flexible electronics. In order to apply flexible devices on the polymer substrates, all layers should require the characteristic of flexibility as well as the low temperature process. Especially, pentacene thin film transistors (TFTs) have been investigated for probable use in low-cost, large-area, flexible electronic applications such as radio frequency identification (RFID) tags, smart cards, display backplane driver circuits, and sensors. Since pentacene TFTs were studied, their electrical characteristics with varying single variable such as strain, humidity, and temperature have been reported by various groups, which must preferentially be performed in the flexible electronics. For example, the channel mobility of pentacene organic TFTs mainly led to change in device performance under mechanical deformation. While some electrical characteristics like carrier mobility and concentration of organic TFTs were significantly changed at the different temperature. However, there is no study concerning multivariable. Devices actually worked in many different kinds of the environment such as thermal, light, mechanical bending, humidity and various gases. For commercialization, not fewer than two variables of mechanism analysis have to be investigated. Analyzing the phenomenon of shifted characteristics under the change of multivariable may be able to be the importance with developing improved dielectric and encapsulation layer materials. In this study, we have fabricated flexible pentacene TFTs on polymer substrates and observed electrical characteristics of pentacene TFTs exposed to tensile and compressive strains at the different values of temperature like room temperature (RT), 40, 50, $60^{\circ}C$. Effects of bending and heating on the device performance of pentacene TFT will be discussed in detail.

  • PDF

Micro to Nano-scale Electrohydrodynamic Nano-Inkjet Printing for Printed Electronics: Fundamentals and Solar Cell Applications

  • Byeon, Do-Yeong
    • Proceedings of the Materials Research Society of Korea Conference
    • /
    • 2011.05a
    • /
    • pp.3.2-3.2
    • /
    • 2011
  • In recent years, inkjet printing technology has received significant attention as a micro/nanofabrication technique for flexible printing of electronic circuits and solar cells, as well for biomaterial patterning. It eliminates the need for physical masks, causes fewer environment problems, lowers fabrication costs, and offers good layer-to-layer registration. To fulfill the requirements for use in the above applications, however, the inkjet system must meet certain criteria such as high frequency jetting, uniform droplet size, high density nozzle array, etc. Existing inkjet devices are either based on thermal bubbles or piezoelectric pumping; they have several drawbacks for flexible printing. For instance, thermal bubble jetting has limitations in terms of size and density of the nozzle array as well as the ejection frequency. Piezoelectric based devices suffer from poor pumping energy in addition to inadequate ejection frequency. Recently, an electrohydrodynamic (EHD) printing technique has been suggested and proposed as an alternative to thermal bubble or piezoelectric devices. In EHD jetting, a liquid (ink) is pumped through a nozzle and a strong electric field is applied between the nozzle and an extractor plate, which induce charges at the surfaces of the liquid meniscus. This electric field creates an electric stress that stretches the meniscus in the direction of the electric field. Once the electric field force is larger than the surface tension force, a liquid droplet is formed. An EHD inkjet head can produce droplets smaller than the size of the nozzle that produce them. Furthermore, the EHD nano-inkjet can eject high viscosity liquid through the nozzle forming tiny structures. These unique features distinguish EHD printing from conventional methods for sub-micron resolution printing. In this presentation, I will introduce the recent research results regarding the EHD nano-inkjet and the printing system, which has been applied to solar cell or thin film transistor applications.

  • PDF

Characterization of an Oxidized Porous Silicon Layer by Complex Process Using RTO and the Fabrication of CPW-Type Stubs on an OPSL for RF Application

  • Park, Jeong-Yong;Lee, Jong-Hyun
    • ETRI Journal
    • /
    • v.26 no.4
    • /
    • pp.315-320
    • /
    • 2004
  • This paper proposes a 10-${\mu}m$ thick oxide layer structure that can be used as a substrate for RF circuits. The structure has been fabricated using an anodic reaction and complex oxidation, which is a combined process of low-temperature thermal oxidation (500 $^{\circ}C$ for 1 hr at $H_2O/O_2$) and a rapid thermal oxidation (RTO) process (1050 ${\circ}C$, for 1 min). The electrical characteristics of the oxidized porous silicon layer (OPSL) were almost the same as those of standard thermal silicon dioxide. The leakage current density through the OPSL of 10 ${\mu}m$ was about 10 to 50 $nA/cm^2$ in the range of 0 to 50 V. The average value of the breakdown field was about 3.9 MV/cm. From the X-ray photo-electron spectroscopy (XPS) analysis, surface and internal oxide films of OPSL prepared by a complex process were confirmed to be completely oxidized. The role of the RTO process was also important for the densification of the porous silicon layer (PSL) oxidized at a lower temperature. The measured working frequency of the coplanar waveguide (CPW) type short stub on an OPSL prepared by the complex oxidation process was 27.5 GHz, and the return loss was 4.2 dB, similar to that of the CPW-type short stub on an OPSL prepared at a temperature of 1050 $^{\circ}C$ (1 hr at $H_2O/O_2$). Also, the measured working frequency of the CPW-type open stub on an OPSL prepared by the complex oxidation process was 30.5 GHz, and the return was 15 dB at midband, similar to that of the CPW-type open stub on an OPSL prepared at a temperature of $1050^{\circ}C$ (1 hr at $H_2O/O_2$).

  • PDF

Development of Technology Mapping Algorithm for CPLD by Considering Time Constraint (시간제약 조건을 고려한 CPLD 기술 매핑 알고리즘 개발)

  • Kim, Hi-Seok;Byun, Sang-Zoon
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.36C no.6
    • /
    • pp.9-17
    • /
    • 1999
  • In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

  • PDF