• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.9
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• pp.944-949
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• 2003

In this paper, the double balance mixer(DBM) for Ku-band LNB using InGaP/GaAs HBT process is suggested for the characteristics of low DC power consumption, low noise figure, low intermodulation distortion and wide dynamic range. The 5 dB conversion gain, 14 dB NF, bandwidth 17.9 GHz and 50.34 dBc IMD are obtained under RF input power of -23 dBm, with bias condition as 3 V and 16 mA. The linearity of InGaP/GaAs HBT, the broad band input matching scheme and the optimization of bias point result in the low IMD, the broad bandwidth and the low power consumption characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.253-259
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• 2005

In this paper, BaSrTiO$_{3}$(BST) thin film tunable interdigital capacitor using low cost silicon substrate instead of expensive single-crystalline substrate is presented. The tunable capacitor in which BST thin film is deposited by PLD has operation frequency and applied bias up to 4 GHz and 50 V, respectively. The maximum tunability in capacitance is found to be 30$\%$, for an applied field of 5 kV/cm at a bias of 50 V. Therefore, it has been shown that the BST microwave tunable capacitor can be integrated onto Si substrate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.8 s.111
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• pp.732-738
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• 2006

Divide-by-2 and divide-by-4 circuits which can operate up to 10 GHz are designed. A design method used in these circuits is the TSPC(True Single Phase Clocking) topology. The structure of the TSPC dividers is very simple because they need only a single clock and purely consist of smalt sized cmos devices. Through measurements, we find the fact that in proportion to the bias voltage, the free running frequency increases and the operation region also moves toward a higher frequency region. For operating conditions of bias voltage $3.0{\sim}4.0V$, input power 16dBm and dcoffset $1.5{\sim}2.0V$, 5 GHz and 2.5 GHz output signals divided by 2 and 4 are measured. The layout size of the divide-by-2 circuit is about $500{\times}500 um^2$($50{\times}40um^2$ except pad interconnection part).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.620-624
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• 2016

In this paper we designed a current mode logic frequency divider to transmit a baseband amplitude modulated signal. From simulation result, we studied input and output waveforms according to the variation of input bias voltage. For the purpose of the verification of the study, we designed a current mode logic frequency divider at 1,400 MHz. The designed frequency divider operates between 100 MHz and 3,000 MHz, for -33 dBm input power. The circuit draws $I_{total}=30mA$ from $V_{DD}=3V$ supply, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.5 was successfully downconverted to 700 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.11
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• pp.1111-1116
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• 2011

In this paper, a 60 GHz bidirectional active phase shifter with 130 nm CMOS is presented by replacing CMOS passive switchs in switched-line type phase shifter with Common Gate Amplifier(bidirectional amplifier). Bidirectional active phase shifter is composed of bidirectional amplifier blocks and passive delay line network blocks. The suitable topology of bidirectional amplifier block is CGA(Common Gate Amplifier) topology and matching circuits of input and output are symmetrical due to design same characteristic of it's forward and reverse way. The direction(forward and reverse way) and amplitude of amplification can be controlled by only one bias voltage($V_{DS}$) using combination bias circuit. And passive delay line network blocks are composed of microstrip line. An 1-bit phase shifter is fabricated by Dongbu HiTek 1P8M 130-nm CMOS technology and simulation results present -3 dB average insertion loss and respectively 90 degree and 180 degree phase shift at 60 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.814-819
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• 2008

In this paper, a design of broadband detectors utilizing two ultra-wideband transitions is described for the first time, and the implementation method and measurement results of the detectors are provided. Two ultra-wideband transitions are used for input/output matching circuits for the diode detectors. Two detectors have been implemented using general Schottky diodes and zero-bias Schottky diodes. With general Schottky diodes, the fabricated detector provides less than 10 dB return loss from 11 GHz to 20 GHz, and the detector sensitivity is 30 mV/mW. The detector with zero-bias Schottky diodes shows significantly higher detection sensitivity(300 mV/mW).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.1-9
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• 2014

In this paper, a reconfigurable polarization patch antenna that uses a Y-shaped feed is proposed. The proposed antenna consists of a square patch, a Y-shaped feeding structure, a PIN diode, and a bias circuit for diode operation. The structural symmetry/asymmetry of the feeding structure is determined by the on/off operation of the PIN diode that inserted into the side of one of the lines of the Y-shaped feeding structure. For the proposed reconfigurable antenna, the two microstrip lines of the feeding structure have the same length when the PIN diode operates in the on state, and the antenna exhibits linear polarization(LP). On the other hand, when the PIN diode operates in the off state, the length of one side line of the feeding structure is relatively shorter than that of the other line. Therefore, the antenna exhibits circular polarization(CP). From the measurement results, it is found that the proposed antenna exhibits good impedance matching and axial ratio. In addition, polarization switching can be easily achieved in the same operating band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.6
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• pp.558-567
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• 1997

Linear power amplifier modules with high-efficiency have been developed for PCS handy phone. These modules were designed using extracted large-signal models of MESFETs and harmonic balance simulation. The modules are intended for low-tier and high-tier at the operation frequency range of 1750 ~ 1780 MHz. For low-tier module, the output power and $IMD_3$ were 23.2 dBm and 31 dBc, respectively, at power-added efficiency of 34% with the supply drain bias of 3.6 V. For high-tier module, the output power and $IMD_3$ were 272.2 dBm and 31 dBc, respectively, at power-added efficiency of 33% with the supply drain bias of 4.2 V. These linear power amplifier modules are suitable for PCS handy phone.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.2
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• pp.183-188
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• 2014

In this paper, the propagation effect of power supply uncertainty on the output of class-F power amplifier has been estimated. Also, a 1.9 GHz, 10 watt class-F power amplifier was measured to verify the estimation and to find the optimal biasing point. By approximating the propagation theory of uncertainties, the propagation effect of bias uncertainty was mathmatically calculated. As a result, the DC biases have propagated uncertainties of 15~70 mW. However, at the optimized bias point, the uncertainty in the output power could be dropped less than 15 mW while the output power has dropped by 0.37 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.5 s.120
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• pp.478-485
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• 2007

In this paper, an unequal 1:N Wilkinson power divider with adjustable dividing ratio is proposed. The proposed unequal power divider is composed of basic Wilkinson structure. It consists of rectangular-shaped defected ground structure (DGS), isolated island pattern in DGS, and varactor diodes of which capacitance depends on bias voltage. The characteristic impedance value of microstrip line having DGS goes up and down by controlling bias voltage for diodes, and consequently the power dividing ratio(N) is adjusted. The obtained N from measurement is $2.59{\sim}10.4$ which mean the proposed divider has adjustable unequal dividing ratio.