• Title/Summary/Keyword: Electrical Isolation

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Fabrication of a Silicon Hall Sensor for High-temperature Applications (고온용 실리콘 홀 센서의 제작)

  • Chung, Gwiy-Sang;Ryu, Ji-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.05b
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    • pp.29-33
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    • 2000
  • This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than ${\pm}6.7{\times}10^{-3}/^{\circ}C$ and ${\pm}8.2{\times}10^{-4}/^{\circ}C$, respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and high-temperature operation.

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Design of the Multisection Impedance Transforming Branch-Line Hybrid Using the Genetic Algorithm (유전자 앨거리즘을 이용한 임피던스 변환 브랜치라인 하이브리드 설계)

  • Lee, Gyeong-U;Lee, Sang-Seol
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.37 no.6
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    • pp.28-35
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    • 2000
  • A design method for a multisection impedance transforming branch-line hybrid using a genetic algorithm suitable for MMIC applications is proposed. In contrast to the previous design methods, an asymmetric structure is introduced to optimize the hybrid. Optimization is performed within the impedance range to achieve the realizable hybrids with a microstrip line in a desired frequency range. This design method is applicable to the hybrid which has the arbitrary power division ratio, impedance transforming ratio, isolation, directivity and bandwidth. The hybrid designed by the proposed method has 3∼10% more bandwidth than the previous results.

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A 24-GHz Wide-IF Down-Conversion Mixer Based on 0.13-μm RFCMOS Technology (0.13-μm RFCMOS 공정 기반 24-GHz 광대역 하향 변환 혼합기)

  • Kim, Dong-Hyun;Rieh, Jae-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.11
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    • pp.1235-1239
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    • 2010
  • In this work, a wideband technique has been proposed that improves the IF bandwidth of mixers and a 24-GHz down-conversion mixer employing the proposed technique has been designed and fabricated based on 0.13-${\mu}m$ RFCMOS technology. The mixer showed the conversion gain of $2.7{\pm}1.5$ dB from DC to 5.25 GHz IF for a fixed LO frequency of 24 GHz. Measured P-1dB and LO-RF isolation was -8.7 dBm and 21 dB, respectively. The mixer draws DC current of 10.6 mA from 1.3 V supply.

Development of Microstructure Pad and Its Performances in STI CMP (미세 표면 구조물을 갖는 패드의 제작 및 STI CMP 특성 연구)

  • Jeong, Suk-Hoon;Jung, Jae-Woo;Park, Ki-Hyun;Seo, Heon-Deok;Park, Jae-Hong;Park, Boum-Young;Joo, Suk-Bae;Choi, Jae-Young;Jeong, Hae-Do
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.3
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    • pp.203-207
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    • 2008
  • Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials. There are many elements such as slurry, polishing pad, process parameters and conditioning in CMP process. Especially, polishing pad is considered as one of the most important consumables because this affects its performances such as WIWNU(within wafer non-uniformity) and MRR(material removal rate). In polishing pad, grooves and pores on its surface affect distribution of slurry, flow and profile of MRR on wafer. A subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure(MS) pad. MS pad is designed to have uniform structure on its surface and manufactured by micro-molding technology. And then STI CMP performances such as pattern selectivity, erosion and comer rounding are evaluated.

A Fuzzy Model Based Sensor Fault Detection Scheme for Nonlinear Dynamic Systems (퍼지모델을 이용한 비선형시스템의 센서고장 검출식별)

  • Lee, Kee-Sang
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.2
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    • pp.407-414
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    • 2007
  • A sensor fault detection scheme(SFDS) for a class of nonlinear systems that can be represented by Takagi-Sugeno fuzzy model is proposed. Basically, the SFDS may be considered as a multiple observer scheme(MOS) in which the bank of state observers and the detection & isolation logic are included. However, the proposed scheme has two great differences from the conventional MOSs. First, the proposed scheme includes fuzzy fault detection observers(FFDO) that are constructed based on the T-S fuzzy model that provides very good approximation to nonlinear dynamic systems. Secondly, unlike the conventional MOS, the FFDOS are driven not parallelly but sequentially according to the predetermined sequence to avoid the massive computational burden, which is known to be the biggest obstacle to the practical application of the multiple observer based FDI schemes. During the operating time, each FFDO generates the residuals carrying the information of a specified fault, and the corresponding fault detection logic unit performs the logical operations to detect and isolate the fault of interest. The proposed scheme is applied to an inverted pendulum control system for sensor fault detection/isolation. Simulation study shows the practical feasibility of the proposed scheme.

Reduced Hybrid Ring Coupler Using Surface Micromachining Technology for 94-GHz MMIC Applications

  • Uhm, Won-Young;Beak, Tae-Jong;Ryu, Keun-Kwan;Kim, Sung-Chan
    • Journal of information and communication convergence engineering
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    • v.14 no.4
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    • pp.246-251
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    • 2016
  • In this study, we developed a reduced 94 GHz hybrid ring coupler on a GaAs substrate in order to demonstrate the possibility of the integration of various passive components and MMICs in the millimeter-wave range. To reduce the size of the hybrid ring coupler, we used multiple open stubs on the inside of the ring structure. The chip size of the reduced hybrid ring coupler with multiple open stubs was decreased by 62% compared with the area of the hybrid ring coupler without open stubs. Performance in terms of the loss, isolation, and phase difference characteristics exhibited no significant change after the use of the multiple open stubs on the inside of the ring structure. The reduced hybrid ring coupler showed excellent coupling loss of $3.87{\pm}0.33dB$ and transmission loss of $3.77{\pm}0.72dB$ in the measured frequency range of 90-100 GHz. The isolation and reflection were -48 dB and -32 dB at 94 GHz, respectively. The phase differences between two output ports were $180^{\circ}{\pm}1^{\circ}$ at 94 GHz.

A Study on STI CMP Characteristics using Microstructure Pad (마이크로 표면 구조물을 갖는 패드의 STI CMP 특성 연구)

  • Jung, Jae-Woo;Park, Ki-Hyun;Jang, One-Moon;Park, Sun-Joon;Jeong, Moon-Ki;Jeong, Hae-Do
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.356-357
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    • 2005
  • Chemical mechanical polishing (CMP) allows the planarization of wafers with two or more materials at their surfaces. Especially, polishing pad is considered as one of the most important consumables because of its properties. Subject of this investigation is to apply CMP for planarization of shallow trench isolation structure using microstructure pad. Microstructure pad is designed to have uniform structure on its surface and fabricated by micro-molding technology. And then STI CMP performances such as oxide dishing and nitride corner rounding are evaluated.

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A Study on the Development and Optimization Design of Isolator by Using the 3D Simulator (3D Simulator를 이용한 아이솔레이터 최적화 설계 및 개발에 관한 연구)

  • Jung Seung-Woo;Choi U-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.17 no.3 s.106
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    • pp.229-238
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    • 2006
  • In this paper, developed study about isolator that after design and optimizes center strip to use 3-D simulator. We use the factor about the change and propose simple mode of the simulation. Design strip line that center frequency is 1.85 GHz by software that use 3-D finite element method(FEM) and confirmed variable. Developed isolator were shown that more than isolation 25 dB, reflection loss has the more than 25 dB and insertion loss does not 0.2 dB. We could confirm that compare with simulation and manufacture sample propertied agrees more than 90 %.

VSB-Based Digital On-Channel Repeater with Interference Cancellation System

  • Lee, Jae-Kwon;Suh, Young-Woo;Choi, Jin-Yong;Seo, Jong-Soo
    • ETRI Journal
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    • v.33 no.5
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    • pp.670-678
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    • 2011
  • This paper investigates the design and performance of a digital on-channel repeater (DOCR) for use in Advanced Television Systems Committee (ATSC) digital television (DTV) broadcasting. The main drawback of a DOCR is the echo interference caused by coupling between transmitter and receiver antennas, which induces system instability and performance degradation. In order to overcome this problem, an echo canceller based on the adaptive echo channel estimation (ECE) technique has been researched and applied for a DOCR. However, in the case of ATSC, the pilot signal, which is used for carrier synchronization, may cause a DC offset error and reduce the isolation performance of the echo canceller for a DOCR in an ATSC network. Moreover, since the multipath fading effect of a radio channel usually occurs in a real environment, it should be minimized to improve the overall performance of a DOCR. Therefore, due to the limited isolation performance of echo canceller and the multipath fading effect, an interference cancellation system (ICS) is proposed for a DOCR in an ATSC network. The performance of the proposed DOCR with an ICS is evaluated by software simulation and hardware test results.

Fabrication and Characteristics of High-sensitivity Si Hall Sensors for High-temperature Applications (고온용 고감도 실리콘 홀 센서의 제작 및 특성)

  • 정귀상;노상수
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.565-568
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    • 2000
  • This paper describes on the temperature characteristics of a SDB(silicon-wafer direct bonding) SOI(silicon-on-insulator) Hall sensor. Using the buried oxide $SiO_2$ as a dielectrical isolation layer, a SDB SOI Hall sensor without pn junction isolation has been fabricated on the Si/$SiO_2$/Si structure. The Hall voltage and the sensitivity of the implemented SOI Hall sensor show good linearity with respect to the applied magnetic flux density and supplied current. In the temperature range of 25 to $300^{\circ}C$, the shifts of TCO(temperature coefficient of the offset voltage) and TCS(temperature coefficient of the product sensitivity) are less than $\pm 6.7$$\times$$10^{-3}$/$^{\circ}C$ and $\pm 8.2$$\times$$10^{-4}$/$^{\circ}C$respectively. These results indicate that the SDB SOI structure has potential for the development of a silicon Hall sensor with a high-sensitivity and hip high-temperature operation.

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