• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2017-2032
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• 2018

This study presents, for the first time, state-of-the art review of the various techniques for the modeling of the electrostatic discharge (ESD) generators for the ESD analysis and testing. After a brief overview of the ESD generator, the study provides an in-depth review of ESD generator modeling (analytical, circuit and numerical modeling) techniques for the contact discharge mode. The proposed techniques for each modeling approach are compared to illustrates their differences and limitations.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• Journal of Power Electronics
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• v.11 no.4
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• pp.568-575
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• 2011

This paper proposes an application of energy storage devices (ESD) for low-voltage ride-through (LVRT) capability enhancement and power smoothening of doubly-fed induction generator (DFIG) wind turbine systems. A grid-side converter (GSC) is used to maintain the DC-link voltage. Meanwhile, a machine-side converter (MSC) is used to control the active and reactive powers independently. For grid disturbances, the generator output power can be reduced by increasing the generator speed, resulting in an increased inertial energy of the rotational body. Design and control techniques for the energy storage devices are introduced, which consist of current and power control loops. Also, the output power fluctuation of the generator due to wind speed variations can be smoothened by controlling the ESD. The validity of the proposed method has been verified by PSCAD/EMTDC simulation results for a 2 MW DFIG wind turbine system and by experimental results for a small-scale wind turbine simulator.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Journal of the Korean Society of Radiology
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• v.6 no.6
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• pp.455-464
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• 2012

This study suggested evaluation of approximately exposure to low-dose ionization radiation from medical images using a computed radiography (CR) system in standard X-ray examination and experimental model can compare diagnostic reference level (DRL) will suggest on optimization condition of guard about medical radiation of low dose space. Entrance surface dose (ESD) cross-measuring by standard dosimeter and optically stimulated luminescence dosimeters (OSLDs) in experiment condition about tube voltage and current of X-ray generator. Also, Hounsfield unit (HU) scale measured about each experiment condition in CR system and after character relationship table and graph tabulate about ESD and HU scale, approximately radiation dose about head, neck, thoracic, abdomen, and pelvis draw a measurement. In result measuring head, neck, thoracic, abdomen, and pelvis, average of ESD is 2.10, 2.01, 1.13, 2.97, and 1.95 mGy, respectively. HU scale is $3,276{\pm}3.72$, $3,217{\pm}2.93$, $2,768{\pm}3.13$, $3,782{\pm}5.19$, and $2,318{\pm}4.64$, respectively, in CR image. At this moment, using characteristic relationship table and graph, ESD measured approximately 2.16, 2.06, 1.19, 3.05, and 2.07 mGy, respectively. Average error of measuring value and ESD measured approximately smaller than 3%, this have credibility cover all the bases radiology area of measurement 5%. In its final analysis, this study suggest new experimental model approximately can assess radiation dose of patient in standard X-ray examination and can apply to CR examination, digital radiography and even film-cassette system.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.565-566
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• 2008

The high efficiency power management IC(PMIC) for Moblie application is proposed in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. The saw-tooth generator is made to have 1.2 MHz oscillation frequency and full range of output swing from ground to supply voltage(VDD:3.3V). The comparator is designed with two stage OP amplifier. And the error amplifier has 70dB DC gain and $64^{\circ}$ phase margin. DC-DC converter, based on Voltage-mode PWM control circuits, achieved the high efficiency near 95% at 100mA output current. DC-DC converter is designed with LDO in stand-by mode which fewer than 1mA for high efficiency.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.