• Journal of Convergence for Information Technology
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• v.10 no.10
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• pp.47-52
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• 2020

The general flatbed printer system is composed of a PC and a dedicated S/W, which is inconvenient to use. In the end, there is a need for a technology that can easily and conveniently use various types of printing through simplification, smartization, etc. of a flatbed printer system configuration. That is, there is an increasing demand for multi-dimensional printer capable of printing on various types of materials with one printer and capable of printing various types of products. Therefore, in this paper, we developed a flatbed printer system capable of multi-dimensional printing using Head Encoder/Trigger control. To this end, we developed a flatbed printer that connects the internal module of the flatbed printer with an input type detection sensor and controls all operating states by the head encoder and head trigger signals of the printer through separate main controllers. Through this, the development and diffusion of IoT technology will expand the printer control of the smart environment to the developed form throughout the industry. It is expected to contribute to the development of the 3D printing industry in the future.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.6
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• pp.109-118
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• 1998

This paper presents an ASIC implementation of video encoder which converts either digital RGB or YCbCr to S-video(Y/C) and composite video signal. The video timing signal of this encoder includes horizontal sync., vertical sync. signal and blanking, and this encoder supports field identification signal which is convenient for video editing. The encoder has been designed in the 4 stages pipeline structure to assure the stable operation of each submodule. The proposed encoder requires only 20K gates ,which is a 40% reduction in hardware compared with [13]. The designed encoder was fabricated in $0.65{\mu}m$ SOG triple metal CMOS technology. Chip size is $3.7478mm {\times} 4.4678mm$ including PAD, gate counts is 19,468 and dissipated power is 0.9W.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.59-65
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• 1999

In this paper, we design a entorpy encoder of HDTV/DTV encoder blocks on the basis of MPEG-II. The designed entropy encoder outputs its bit stream at 9Mbps bit rate inserting zero-stepping block to protect the depletion of buffer in case that the generated bit stream is stored in buffer and uses not only PROM bit combinational circuit to solve the problem of critical path, and packer block, one of submerge, is designed to packing into 24 bit unit using barrel shifter, and it is constructed to blocks of header information encoder, input information delay, submerge, and buffer control. Designed circuits is verified by VHDL function simulation, as a result of performing P&R with Gate compiler that apply $0.8{\mu}m$ Gate Array specification, pin and gate number of total circuits has been tested to each 235 and about 120,000.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.12
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• pp.61-67
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• 2000

In switched reluctance motor(SRM) drive, it is necessary to synchronize the stator phase excitation with the rotor position. Therefore the rotor position information is an essential. Usually optical encoders or resolvers are used to provide the rotor position information. These sensors are expensive and are not suitable for high speed operation. In general, the accuracy of the switching angle is dependent upon the resolution of the encoder and the sampling period of the microprocessor. But the region of high speed, switching angles are fluctuated back and forth from the preset values, which are cause by the sampling period of the microprocessor. Therefore, the low cost linear encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using the simple digital logic circuit is also presented in this paper. It is verified from the experiments that the proposed encoder and logic controller can be a powerful candidate for the practical low cost SRM drive.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.88-94
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• 2005

This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.4
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• pp.319-326
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• 2002

In switched reluctance motor(SRM) drive, it is important to synchronize the stator phase excitation with the rotor position; therefore, the information about rotor position is essential. Generally, optical encoders or resolvers are used to provide the information. However, these sensors are expensive and are not suitable for high-speed operation. The accuracy of the switching angles is dependent upon the resolution of the encoder and the sampling period of the microprocessor. In the high-speed region, switching angles are fluctuated back and forth out of the preset value, which is caused by the sampling period of the microprocessor. In this paper, a low cost linear encoder suitable far the practical and stable SRM drive is proposed and also the control algorithm to generate the switching signals using a simple digital logic is presented. The validity of the proposed linear encoder with a proper logic controller is verified through the experiments.

• Journal of Biomedical Engineering Research
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• v.35 no.1
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• pp.8-13
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• 2014

In this paper, the gait imbalance evaluation algorithm based on temporal symmetry ratio using encoder is proposed. The device is attached to the hip joint in order to measure the angle during the normal gait. Using an angle data, the stance phase and swing phase was determined. And the value of TSR(temporal symmetry ratio) was calculated by stance phase and swing phase of gait cycle. For the comparative experiment, the conventional method of the foot pressure was measured at the same conditions. The results of statistical analysis, there was a significant difference (p < 0.05) when using encoder. The gait imbalance analysis using encoder is effective in determining the imbalance than using the existing method of pressure.

• Aerospace Engineering and Technology
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• v.8 no.1
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• pp.179-186
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• 2009

This paper describes the design and implementation for spread spectrum FTS encoder and decoder. The FTS command format is defined by 64 bit encrypted packet that contains all required information relayed between the ground and the vehicle. Encryption is accomplished using the Tripple-DES encryption algorithm in block encryption form. The proposed FTS encoder and decoder is using the Convolution Encoding and Viterbi Decoding for forward error correction. The Spread Spectrum Modulation is done using a PN code, which is 256 bit gold code. The simulation result shows that the designed FTS decoder is compatible with the designed FTS encoder.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.1
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• pp.30-35
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• 2004

In a switched reluctance motor drive, it is important to synchronize the stator phase excitation with the rotor position, Therefore the position of rotor is an essential information. Although high resolution optical encoder/resolvers we used to provide a precise position information, these sensors are expensive. And switching angles synchronizing using sensorless technique has some problems like a reliability and fluctuating of the preset value in the high-speed region, which is caused by the sampling period of the microprocessor. In this paper, a low cost analog encoder suitable for practical applications is proposed. And the control algorithm to generate switching signals using a simple digital logic is presented. The validity of the proposed analog encoder with a proper logic controller is verified from the experiments.