• Journal of the Korea Concrete Institute
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• v.27 no.5
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• pp.541-549
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• 2015

This study was conducted to experimentally investigate the seismic retrofitting performance of non-ductile reinforced concrete (RC) frames by introducing engineered cementitious composite (ECC) wing panel elements. Non-ductile RC frame tested in this study were designed and detailed for gravity loads with insufficient or no consideration to lateral loads. Therefore, Non-ductile RC frame were not satisfied on present seismic code requirements. The precast ECC wing panels were used to improve the seismic structural performance of existing non-ductile RC frame. A series of experiments were carried out to evaluate the structural performance of ECC wing panel elements alone a non-ductile RC frame strengthened by adding ECC panel elements. Failure pattern, strength, stiffness and energy dissipation characteristics of specimens were evaluated based on the test results. The test results show that both lateral strength and stiffness were significantly improved in specimen strengthened than non-ductile RC frame. It is noted that ECC wing wall elements application on non-ductile RC frame can be effective alternative on seismic retrofit of non-ductile building.

• Nuclear Engineering and Technology
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• v.34 no.5
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• pp.421-432
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• 2002

As one of the advanced design features of the APR1400, direct vessel injection (DVI) system is being considered instead of conventional cold leg injection (CLI) system. It is known that the DVI system greatly enhances the reliability of the emergency core cooling (ECC) system. However, there is still a dispute on its performance in terms of water delivery to the reactor core during the reflood phase of a large-break loss-of-coolant accident (LOCA). Thus, experimental validation is under progress. In this paper, test results of direct ECC bypass performed in the steam-water test facility tailed MIDAS (Multi-dimensional Investigation in Downcomer Annulus Simulation) are presented. The test condition is determined, based on the preliminary analysis of TRAC code, by applying the ‘modified linear scaling method’with the l/4.93 length scale . From the tests, ECC direct bypass fraction, steam condensation rate and information on the flow distribution in the upper annulus downcomer region are obtained.

• The Transactions of the Korea Information Processing Society
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• v.7 no.5
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• pp.1491-1499
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• 2000

This paper is designed and implemented the data recovery mechanism for 2-D (2-dimensional) bar code system. The data recovery algorithm used the modified Reed-Solomon algorithm and it is implemented into 2-D bar code system. There are 7 types of 2-D bar code system, which are 21x21, 25x25, 41x41, 73x73, 101x101, 177x177. This paper has been experimented that how many data is saved among several 2-D bar code types and how many data re recovered. In the first experiment, the big size 2-D bar code system has many ECC codeword. Therefore, original data cannot be assigned to 2-D bar code system. In the second experiment, even if 35∼40% loss dta for the 2-D bar code system, the 2-D bar code system could have been recovered to original data.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.537-540
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• 2003

In this paper, we evaluated error correction performance and recording density of an optical disc system. The performance of Low-Density Parity Check code (LDPC) is compared to the HD-DVD (BD) ECC. The recording density of optical disc can be increased by reducing the redundancy of the user data. Moreover, since the correction capability of LDPC with decreased redundancy is better than that of BD, the recording density can also be increased by reducing the mark length of the data on the disc surface.

• Nuclear Engineering and Technology
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• v.43 no.3
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• pp.257-270
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• 2011

A set of reflood tests has been performed using ATLAS, which is a thermal-hydraulic integral effect test facility for the pressurized water reactors of APR1400 and OPR1000. Several important phenomena were observed during the ATLAS LBLOCA reflood tests, including core quenching, down-comer boiling, ECC bypass, and steam binding. The present paper discusses those four topics based on the LB-CL-11 test, which is a best-estimate simulation of the LBLOCA reflood phase for APR1400 using ATLAS. Both homogeneous bottom quenching and inhomogeneous top quenching were observed for a uniform radial power profile during the LB-CL-11 test. From the observation of the down-comer boiling phenomena during the LB-CL-11 test, it was found that the measured void fraction in the lower down-comer region was relatively smaller than that estimated from the RELAP5 code, which predicted an unrealistically higher void generation and magnified the downcomer boiling effect for APR1400. The direct ECC bypass was the dominant ECC bypass mechanism throughout the test even though sweep-out occurred during the earlier period. The ECC bypass fractions were between 0.2 and 0.6 during the later test period. The steam binding phenomena was observed, and its effect on the collapsed water levels of the core and down-comer was discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.43-49
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• 2008

In this paper, a method using the Ant Colony Optimization(ACO) is proposed for reducing the power consumption of memory ECC checker circuitry which provide Single-Error Correcting and Double-Error Detecting(SEC-DED). The H-matrix which is used to generate SEC-DED codes is optimized to provide the minimum switching activity with little to no impact on area or delay using the symmetric property and degrees of freedom in constructing H-matrix of Hsiao codes. Experiments demonstrate that the proposed method can provide further reduction of power consumption compared with the previous works.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Aerospace Engineering and Technology
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• v.3 no.1
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• pp.197-204
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• 2004

A design of regenerative cooling system of 30 ton level thrust combustion chamber for ground test has been performed. The 1-D design code has been validated by comparing with the heat flux of the NAL calorimeter for high chamber pressure and water-cooling performance of the ECC engine of MOBIS. The present design code has been confirmed to predict accurately the heat flux and water-cooling performance for high chamber pressure condition. The maximum hot-gas-side wall temperature is predicted to be about 720 K without thermal barrier coating and the coolant-side wall temperature is less than the coking temperature of RP-1. The coolant temperature rises nearly 100 K with thermal barrier coating when Jet-A1 is used as coolant.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.601-606
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• 2017

SRAM-based FPGAs mainly used to develop and implement high-performance circuits have SRAM-type configuration memory. Soft errors in memory devices are the main threat from a reliability point of view. Soft errors occurring in the configuration memory of FPGAs cause FPGAs to malfunction. SEM(Soft Error Mitigation) Controllers offered by Xilinx can mitigate the influence of soft errors in configuration memory. SEM Controllers use ECC(Error Correction Code) and CRC(Cyclic Redundancy Code) which are placed around the configuration memory to detect and correct the errors. The correction is done through a partial reconfiguration process. This paper presents the availability analysis of SRAM-based FPGAs against soft errors under the protection of SEM Controllers. Availability functions were derived and compared according to the correction capability of SEM Controllers of several different families of FPGAs. The result may help select an SRAM-based FPGA part and estimate the availability of FPGAs running in an environment where soft errors occur.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.10C
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• pp.798-804
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• 2008

This paper proposes a low-power circuit for detecting and correcting L2 cache errors during microprocessor data image processing. A simplescalar-ARM is used to analyze input and output data by accessing the microprocessor's L2 cache during image processing in terms of the data input and output frequency as well as the variation of each bit for 32-bit processing. The circuit is implemented based on an H-matrix capable of achieving low power consumption by extracting bits with small and large amounts of variation and allocating bits with similarities in variation. Simulation is performed using H-spice to compare power consumption of the proposed circuit to the odd-weight-column code used in a conventional microprocessor. The experimental results indicated that the proposed circuit reduced power consumption by 17% compared to the odd-weight-column code.