• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

• Journal of the Korea Computer Graphics Society
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• v.4 no.1
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• pp.55-66
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• 1998

This paper presents a simple method for relieving the ambiguity problems within the sub-voxel based surface-fitting approach for the surface construction. ECB algorithm is proposed to avoid the ambiguity problem which is the root of the holes within the resulting polygon based approximation. The basic idea of our disambiguation strategy is the use of a set of predefined modeling primitives (we call SMP) which guarantees the topological consistency of resulted surface polygons. 20 SMPs are derived from the extension of the concept of the elementary modeling primitives in the CB algorithm [3], and fit one to five faces of them to the iso-surface crossing a cell with no further processing. A look-up table which has a surface triangle list is pre-calculated using these 20 SMPs. All of surface triangles in the table are from the faces of SMPs and are stored in the form of edge list on which vertices of each surface triangle are located. The resulted polygon based approximation is unique at every threshold value and its validity is guaranteed without considering the complicated problems such as average of density and postprocessing. ECB algorithm could be free from the need for the time consuming post-processing, which eliminates holes by revisiting every boundary cell. Through three experiments of surface construction from volume data, its capability of hole avoidance is showed.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.11b
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• pp.110-115
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• 2002

In this paper, the results of an analysis of the dynamic behavior of the eddy current brake(ECB) system are presented. The measured irregularity of the track in Korean high speed line and the track irregularity given by ERRI(high level) were used for simulation. The wheel-rail profile combination were analyzed with different rail gauges. A model of the bogie with an substitute body for the carbody was implemented in the Multi-body-Simulation Program SIMPACK. The ECB frame was modelled both as flexible body and as rigid body. Four different driving conditions were analyzed. In this study dynamic behavior in general were performed to evaluate the design of eddy current brake system and specially the effect of damper was also studied. A comparison of simulations with and without damper shows that the damper have most effect for lower speed. The simulation results will be verified by comparison with measured data from on line test and also used for improving design.

• Journal of Microbiology and Biotechnology
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• v.19 no.7
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• pp.666-674
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• 2009

An electrochemical bioreactor (ECB) composed of a cathode compartment and an air anode was used in this study to characterize the ethanol fermentation of Zymomonas mobilis. The cathode and air anode were constructed of modified graphite felt with neutral red (NR) and a modified porous carbon plate with cellulose acetate and porous ceramic membrane, respectively. The air anode operates as a catalyst to generate protons and electrons from water. The growth and ethanol production of Z. mobilis were 50% higher in the ECB than were observed under anoxic nitrogen conditions. Ethanol production by growing cells and the crude enzyme of Z. mobilis were significantly lower under aerobic conditions than under other conditions. The growing cells and crude enzyme of Z. mobilis did not catalyze ethanol production from pyruvate and acetaldehyde. The membrane fraction of crude enzyme catalyzed ethanol production from glucose, but the soluble fraction did not. NADH was oxidized to $NAD^+$in association with $H_2O_2$reduction, via the catalysis of crude enzyme. Our results suggested that NADH/$NAD^+$balance may be a critical factor for ethanol production from glucose in the metabolism of Z. mobilis, and that the metabolic activity of both growing cells and crude enzyme for ethanol fermentation may be induced in the presence of glucose.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.237-240
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• 2012

This paper describes an implementation of ARIA crypto algorithm which is a KS (Korea Standards) block cipher algorithm. The ARIA crypto-core supports three master key lengths of 128/192/256-bit specified in the standard and the four modes of operation including ECB, CBC, CTR and OFB. To reduce hardware complexity, a hardware sharing is employed, which shares round function in encryption/decryption module with key initialization module. The ARIA crypto-core is verified by FPGA implementation, the estimated throughput is about 1.07 Gbps at 167 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.5
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• pp.317-322
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• 2014

Data security and integrity is a critical issue in data transmission over wired/wireless links. A large amount of data is encrypted before transmission, by block cipher using mode of operation. RBF mode is a block cipher mode of operation which uses random characteristics. In this paper, we analyze the safety against known plaintext attack and chosen plaintext attack of RBF mode compared to the traditional modes. According to the analysis, RBF mode is known to be secure while the traditional modes are not secure against them.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1164-1174
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• 1992

In this paper, an Information Security protocol in LLC/MAC Layer Architecture is discussed. This paper examines the security Vulnerability and threats, the security Service required to protect these threats, and architectural considerations of security protocol in IEEE 802 LAN architecture. To provide an Information security service, an information security protocol(SP2 : Security Protocol 2) PDU construction with LLC/MAC service primitives is suggested. To construct the SP2 protocol, the ECB, CBC mode of DES algorithm and DAA(Data Authentication Algorithm) of FIPS is used. The SP2 protocol suggested in this paper provides data origin authentication, data confidentiality, data integrity service.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.778-784
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• 2012

A symmetric block cryptosystem uses an identical cryptographic key at encryption and decryption processes. HIGHT cipher algorithm is 64-bit block cryptographic technology for mobile device that was authorized as international standard by ISO/IEC on 2010. In this paper, block cipher HIGHT algorithm is designed using Verilog-HDL. Four modes of operation for block cipher such as ECB, CBC, OFB and CTR are supported. When continuous message blocks of fixed size are encrypted or decrypted, the desigend HIGHT core can process a 64-bit message block in every 34-clock cycle. The cryptographic processor designed in this paper operates at 144MHz on vertex chip of Xilinx, Inc. and the maximum throughput is 271Mbps. The designed cryptographic processor is applicable to security module of the areas such as PDA, smart card, internet banking and satellite broadcasting.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.