• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.54.2-54.2
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• 2010

최근까지는 주로 비정질 실리콘이 디스플레이의 채널층으로 상용화 되어왔다. 비정질 실리콘 기반의 박막 트랜지스터는 제작의 경제성 및 균일성을 가지고 있어서 널리 상용화되고 있다. 하지만 비정질 실리콘의 구조적인 문제인 낮은 전자 이동도(< $1\;cm^2/Vs$)로 인하여 디스플레이의 대면적화에 부적합하며, 광학적으로 불투명한 특성을 갖기 때문에 차세대 디스플레이의 응용에 불리한 점이 있다. 이런 문제점의 대안으로 현재 국내외 여러 연구 그룹에서 산화물 기반의 반도체를 박막 트랜지스터의 채널층으로 사용하려는 연구가 진행중이다. 산화물 기반의 반도체는 밴드갭이 넓어서 광학적으로 투명하고, 상온에서 증착이 가능하며, 비정질 실리콘에 비해 월등히 우수한 이동도를 가짐으로 디스플레이의 대면적화에 유리하다. 특히 Zinc Oxide의 경우, band gap이 3.4eV로써, transparent conductors, varistors, surface acoustic waves, gas sensors, piezoelectric transducers 그리고 UV detectors 등의 많은 응용에 쓰이고 있다. 또한, a-Si TFTs에 비해 ZnO-based TFTs의 경우 우수한 소자 성능과 신뢰성을 나타내며, 대면적 제조시 우수한 균일성 및 낮은 생산비용이 장점이다. 그러나 ZnO-baesd TFTs의 경우 일정한 bias 아래에서 threshold voltage가 이동하는 문제점이 displays의 소자로 적용하는데 매우 중요하고 문제점으로 여겨진다. 특히 gate insulator와 channel layer사이의 interface에서의 defect에 의한 charge trapping이 이러한 문제점들을 야기한다고 보고되어진다. 본 연구에서는 Zinc Oxide 기반의 박막 트랜지스터를 DC magnetron sputtering을 이용하여 상온에서 제작을 하였다. 또한, $Si_3N_4$ 기판 위에 electron cyclotron resonance (ECR) $O_2$ plasma 처리와 plasma-enhanced chemical vapor deposition (PECVD)를 통하여 $SiO_2$ 를 10nm 증착을 하여 interface의 개선을 시도하였다. 그리고 TFTs 소자의 출력 특성 및 전이 특성을 평가를 하였고, 소자의 field effect mobility의 값이 향상을 하였다. 또한 Temperature, Bias Temperature stability의 조건에서 안정성을 평가를 하였다. 이러한 interface treatment는 안정성의 향상을 시킴으로써 대면적 디스플레의 적용에 비정질 실리콘을 대체할 유력한 물질이라고 생각된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.159-160
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• 2012

지난 30년 동안 플래시 메모리의 주류 역할을 하였던 부유 게이트 플래시 메모리는 40 nm 기술 노드 이하에서 셀간 간섭, 터널 산화막의 누설전류 등에 의한 오동작으로 기술적 한계를 맞게 되었다. 또한 기존의 비휘발성 메모리는 동작 시 높은 전압을 요구하므로 전력소비 측면에서도 취약한 단점이 있다. 그러나 이러한 문제점들을 기존의 Si기반의 소자기술이 아닌 새로운 재료나 공정을 통해서 해결하려는 연구가 최근 활발하게 진행되고 있다. 특히, 플래시 메모리의 중요한 구성요소의 하나인 터널 산화막은 메모리 소자의 크기가 줄어듦에 따라서 SiO2단층 구조로서는 7 nm 이하에서 stress induced leakage current (SILC), 직접 터널링 전류의 증가와 같은 많은 문제점들이 발생한다. 한편, 기존의 부유 게이트 타입의 메모리를 대신할 것으로 기대되는 전하 포획형 메모리는 쓰기/지우기 속도를 향상시킬 수 있으며 소자의 축소화에도 셀간 간섭이 일어나지 않으므로 부유 게이트 플래시 메모리를 대체할 수 있는 기술로 주목받고 있다. 특히, TBM (tunnel barrier engineered memory) 소자는 유전율이 큰 절연막을 적층하여 전계에 대한 터널 산화막의 민감도를 증가시키고, 적층된 물리적 두께의 증가에 의해 메모리의 데이터 유지 특성을 크게 개선시킬 수 있는 기술로 관심이 증가하고 있다. 본 연구에서는 Si3N4/Ta2O5를 적층시킨 staggered구조의 tunnel barrier를 제안하였고, Si기판 위에 tunnel layer로 Si3N4를 Low Pressure Chemical Vapor Deposition (LPCVD) 방법과 Ta2O5를 RF Sputtering 방법으로 각각 3/3 nm 증착한 후 e-beam evaporation을 이용하여 게이트 전극으로 Al을 150 nm 증착하여 MIS- capacitor구조의 메모리 소자를 제작하여 동작 특성을 평가하였다. 또한, Si3N4/Ta2O5 staggered tunnel barrier 형성 후의 후속 열처리에 따른 전기적 특성의 개선효과를 확인하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.148-149
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• 2012

This paper reports doping of carbon atoms in GaN layer, which based on dimethylhydrazine (DMHy) and growth temperature. It is well known that dislocations can act as non-radiative recombination center in light emitting diode (LED). Recently, many researchers have tried to reduce the dislocation density by using various techniques such as lateral epitaxial overgrowth (LEO) [1] and patterned sapphire substrate (PSS) [2], and etc. However, LEO and PSS techniques require additional complicated steps to make masks or patterns on the substrate. Some reports also showed insertion of carbon doped layer may have good effect on crystal quality of GaN layer [3]. Here we report the growth of GaN epitaxial layer by inserting carbon doped GaN layer into GaN epitaxial layer. GaN:C layer growth was performed in metal-organic chemical vapor deposition (MOCVD) reactor, and DMHy was used as a carbon doping source. We elucidated the role of DMHy in various GaN:C growth temperature. When growth temperature of GaN decreases, the concentration of carbon increases. Hence, we also checked the carbon concentration with DMHy depending on growth temperature. Carbon concentration of conventional GaN is $1.15{\times}1016$. Carbon concentration can be achieved up to $4.68{\times}1,018$. GaN epilayer quality measured by XRD rocking curve get better with GaN:C layer insertion. FWHM of (002) was decreased from 245 arcsec to 234 arcsec and FWHM of (102) decreased from 338 arcsec to 302 arcsec. By comparing the quality of GaN:C layer inserted GaN with conventional GaN, we confirmed that GaN:C interlayer can block dislocations.

• Current Photovoltaic Research
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• 제2권3호
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• pp.103-109
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• 2014

Highly efficient hydrogenated nanocrystalline silicon (nc-Si:H) thin-film solar cells were prepared on flexible stainless steel substrates using plasma-enhanced chemical vapor deposition. To enhance the performance of solar cells, material properties of back reflectors, n-doped seed layers and wide bandgap nc-SiC:H window layers were optimized. The light scattering efficiency of Ag back reflectors was improved by increasing the surface roughness of the films deposited at elevated substrate temperatures. Using the n-doped seed layers with high crystallinity, the initial crystal growth of intrinsic nc-Si:H absorber layers was improved, resulting in the elimination of the defect-dense amorphous regions at the n/i interfaces. The nc-SiC:H window layers with high bandgap over 2.2 eV were deposited under high hydrogen dilution conditions. The vertical current flow of the films was enhanced by the formation of Si nanocrystallites in the amorphous SiC:H matrix. Under optimized conditions, a high conversion efficiency of 9.13% ($V_{oc}=0.52$, $J_{sc}=25.45mA/cm^2$, FF = 0.69) was achieved for the flexible nc-Si:H thin-film solar cells.

• Applied Science and Convergence Technology
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• 제23권5호
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• pp.248-253
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• 2014

Air Gap Membrane Distillation (AGMD) is one of several technologies that can be used to solve problems fresh water availability. AGMD exhibits several advantages, including low conductive heat loss and higher thermal efficiency, due to the presence of an air gap between the membrane and condensation wall. A previous study by Bhardwaj found that the condensation surface properties (materials and contact angle) affected the total collected fresh water in the solar distillation process. However, the process condition differences between solar distillation and AGMD might result in different condensation phenomena. In contrast, N. Miljkovic showed that a hydrophobic surface has higher condensation heat transfer. Moreover, to the best of our knowledge, there is no study that investigates the effect of condensation surface properties in AGMD to overall process performance (i.e. flux and thermal efficiency). Thus, in this study, we treated the AGMD condensation surface to make it hydrophobic or hydrophilic. The condensation surface could be made hydrophilic by immersing and boiling plate in deionized (DI) water, which caused the formation of hydrophilic aluminum hydroxide (AlOOH) nanostructures. Afterwards, the treated plate was coated using hexamethyldisiloxane (HMDSO) through plasma-enhanced chemical vapor deposition (PECVD). The result indicated that condensation surface properties do not affect the permeate flux or thermal efficiency significantly. In general, the permeate flux and thermal efficiency for the treated plates were lower than those of the non-treated plate (pristine). However, at a 1 mm and 3 mm air gap, the treated plate outperformed the non-treated plate (pristine) in terms of permeate flux. Therefore, although surface wettability effect was not significant, it still provided a little influence.

• 한국세라믹학회지
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• 제43권11호
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• pp.688-692
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• 2006

Ferroelectric lanthanides-substituted $Bi_4Ti_3O_{12}$ $(Bi_{4-x}Ln_xTi_3O_{12}, BLnT)$ thin films approximately 200 nm in thickness were deposited by metal organic chemical vapor deposition onto Pt(111)/Ti/SiO$_2$/Si(100) substrates. Many researchers reported that the lanthanides substitution for Bi in the pseudo-perovskite layer caused the distortion of TiO$_6$ octahedron in the a-b plane accompanied with a shift of the octahedron along the a-axis. In this study, the effect of lanthanides (Ln=Pr, Eu, Gd, Dy)-substitution and crystallization temperature on their ferroelectric properties of bismuth titanate $(Bi_4Ti_3O_{12}, BIT)$ thin films were investigated. As BLnT thin films were substituted to lanthanide elements (Pr, Eu, Gd, Dy) with a smaller ionic radius, the remnant polarization (2P$_r$) values had a tendency to increase and made an exception of the Eu-substituted case because $Bi_{4-x}Eu_xTi_3O_{12}$ (BET) thin films had the smaller grain sizes than the others. In this study, we confirmed that better ferroelectric properties can be expected for films composed of larger grains in bismuth layered peroskite materials. The crystallinity of the thin films was improved and the average grain size increased as the crystallization temperature,increased from 600 to 720$^{\circ}C$. Moreover, the BLnT thin film capacitor is characterized by well-saturated polarization-electric field (P-E) curves with an increase in annealing temperature. The BLnT thin films exhibited no significant degradation of switching charge for at least up to $1.0\times10^{11}$ switching cycles at a frequency of 1 MHz. From these results, we can suggest that the BLnT thin films are the suitable dielectric materials for ferroelectric random access memory applications.

• 한국재료학회지
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• 제10권10호
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• pp.691-697
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• 2000

자외선 검출소자로 응용될 수 있는 우수한 특성을 지진 $Al_xGa_{1-x}N$ 박막을 MOCVD 법으로 성장시킨 후 박막의 구조적인 특성을 조사하였다. 사파이어 기판 위에 성장된 $Al_xGa_{1-x}N$의 물리적인 특성을 평가하기 위해 Synchrotron Radiation XRD를 사용하였다. $Al_xGa_{1-x}N$의 두께가 커질수록 박막의 결정성은 증가하였으며 아래층은 Undoped GaN의 결정성과 성장된 $Al_xGa_{1-x}N$의 결정성이 서로 비례적인 상관관계를 가지고 있음을 알아내었다. Al 조성비는 막질에 크게 영향을 주었으며 조성비가 높아질수록 표면 형상은 매우 나빠졌다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.