• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.4
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• pp.93-99
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• 2008

Portable devices generally have limited energy sources, so there is a need to minimize the power consumption of processor using energy conservation methods. One of the most common energy conservation methods is dynamic voltage scaling (DVS). In this paper, we propose a new DVS algorithm which uses workload of application to determine frequency and voltage of processors. The posed DVS algorithm consists of DVS module in kernel and specified function in application. The DVS module monitors the processor utilization and changes frequency and voltage periodically. The other part monitors workload of application. With these two procedures, the processor can change the performance level to meet their deadline while consuming less energy. We implemented the proposed DVS algorithm on PXA270 processor with Linux 2.6 kernel.

• Journal of Computing Science and Engineering
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• v.4 no.3
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• pp.189-206
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• 2010

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications in embedded system design. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of tasks to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In addition, DVS needs to be carefully applied so that the dynamically varying chip temperature should not exceed a certain threshold because a drastic increase of chip temperature is highly likely to cause system function failure. This paper reviews representative works on the theoretical solutions to DVS problems regarding inter-task DVS, intra-task DVS, voltage transition, and thermal-aware DVS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.428-430
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.544-546
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• 2006

This paper proposes a new means of performance optimization for multimedia algorithm utilizing the Microscopic DVS (Dynamic Voltage Scaling). The Microscopic DVS technique controls the operating frequency and the supply voltage levels dynamically according to the processing requirement for each frame of multimedia data. The huffman decoding algorithm of MPEG-2 AAC audio decoder is optimized to maximize the power saving efficiency of Microscopic DVS technique. The experimental results show the reduction of computational complexity by more than 30% and the reduction of power consumption by more than 17% compared with those of the conventionally fast method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.3
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• pp.421-428
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• 2008

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. As using slack times, it extends the execution time of the big load operations by changing the frequency and the voltage of variable voltage processors. Researches, that controlling the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system, have been going on. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose the new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS algorithm can improve the energy efficiency of the entire system because it controls frequency and voltages having the data dependency among processors.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.736-748
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• 2003

Dynamic voltage scaling(DVS), which adjusts the clock speed and supply voltage dynamically, is an effective technique in reducing the energy consumption of embedded real-time systems. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. In this paper, we propose novel DVS algorithms for periodic hard real-time tasks based on an improved slack estimation algorithm. Unlike the existing techniques, the proposed method can be applied to most priority-driven scheduling policies. Especially, we apply the proposed slack estimation method to EDF and RM scheduling policies. The experimental results show that the DVS algorithms using the proposed slack estimation method reduce the energy consumption by 20∼40 % over the existing DVS algorithms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2942-2944
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• 2005

마이크로 프로세서의 클럭 속도를 공급 전압에 따라 변하게 하는 방법을 Dynamic Voltage Scaling 방법이라 한다. 이것은 운영체제를 내장한 컴퓨터 시스템의 에너지 소비 효율성을 높일 수 있는 매우 효과적인 방법이다. 본 논문에서는 Dynamic Voltage Scaling 방법을 응용하여 실시간 운영체제의 스케줄링 방법을 제안하였다. 이 방법은 다음에 실행할 태스크의 양을 예하여 적절하게 공급전압과 클럭 속도를 조절함으로써 에너지 소비 효율성을 높였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.866-874
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• 2006

This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.