• Nuclear Engineering and Technology
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• v.54 no.7
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• pp.2453-2466
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• 2022

Nuclear power plant operators in the main control room are exposed to stressful conditions in emergency situations as immediate and appropriate mitigations are required. While emergency operating procedures (EOPs) provide operators with the appropriate tasks and diagnostic guidelines, EOPs have static properties that make it difficult to reflect the dynamic changes of the plant. Due to this static nature, operator workloads increase because unrelated information must be screened out and numerous displays must be checked to obtain the plant status. Generally, excessive workloads should be reduced because they can lead to human errors that may adversely affect nuclear power plant safety. This paper presents a framework for an operator support system that can substitute the initial responses of the EOPs, or in other words the immediate actions and diagnostic procedures, in the early stages of an emergency. The system assists operators in emergency operations as follows: performing the monitoring tasks in parallel, identifying current risk and latent risk causality, diagnosing the accident, and displaying all information intuitively with a master logic diagram. The risk causalities are analyzed with a functional modeling methodology called multilevel flow modeling. This system is expected to reduce workloads and the time for performing initial emergency response procedures.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.58-65
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• 2015

This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.7
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• pp.1455-1462
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• 2012

In this paper, a BCD process based high-reliability 24-bit dual-port eFuse OTP Memory for PMICs is designed. We propose a comparison circuit at program-verify-read mode to test that the program datum is correct by using a dynamic pseudo NMOS logic circuit. The comparison result of the program datum with its read datum is outputted to PFb (pass fail bar) pin. Thus, the normal operation of the designed OTP memory can be verified easily by checking the PFb pin. Also we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse at program-verify-read mode. We design a 24-bit eFuse OTP memory which uses Magnachip's $0.35{\mu}m$ BCD process, and the layout size is $289.9{\mu}m{\times}163.65{\mu}m$ ($=0.0475mm^2$).

• Journal of Internet Computing and Services
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• v.19 no.5
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• pp.21-31
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• 2018

Cyber penetration attacks can not only damage cyber space but can attack entire infrastructure such as electricity, gas, water, and nuclear power, which can cause enormous damage to the lives of the people. Also, cyber space has already been defined as the fifth battlefield, and strategic responses are very important. Most of recent cyber attacks are caused by malicious code, and since the number is more than 1.6 million per day, automated analysis technology to cope with a large amount of malicious code is very important. However, it is difficult to deal with malicious code encryption, obfuscation and packing, and the dynamic analysis technique is not limited to the performance requirements of dynamic analysis but also to the virtual There is a limit in coping with environment avoiding technology. In this paper, we propose a machine learning based malicious code analysis technique which improve the weakness of the detection performance of existing analysis technology while maintaining the light and high-speed analysis performance applicable to commercial endpoints. The results of this study show that 99.13% accuracy, 99.26% precision and 99.09% recall analysis performance of 71,000 normal file and malicious code in commercial environment and analysis time in PC environment can be analyzed more than 5 per second, and it can be operated independently in the endpoint environment and it is considered that it works in complementary form in operation in conjunction with existing antivirus technology and static and dynamic analysis technology. It is also expected to be used as a core element of EDR technology and malware variant analysis.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.60-70
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• 2000

An 8$\times$8+20-bit MAC is designed with low power design methodologies at each of the system design levels. At algorithm level, a new method for multipl $y_tract operation is proposed, and it saves the transistor counts over conventional methods in hardware realization. A new Booth selector circuit using NMOS pass-transistor logic is also proposed at circuit level. It is superior to other circuits designed by CMOS in power-delay-product. And at architecture level, we adopted an ELM adder that is known to be the most efficient in power consumption, operating frequency, area and design regularity as the final adder. For registers, dynamic CMOS single-edge triggered flip-flops are used because they need less transistors per bit. To increase the operating frequency 2-stage pipeline architecture is adopted, and fast 4：2 compressors are applied in Wallace tree block. As a simulation result, the designed MAC in 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS process is operated at 200MHz, 3.3V and consumed 35㎽ of power in multiply operation, and operated at 100MHz consuming 29㎽ in MAC operations, respectively.ly.

• Journal of the Korean Institute of Intelligent Systems
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• v.3 no.2
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• pp.18-35
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• 1993

The water level control system of the steam generator in a pressurized water reactor and its control problems are analysed. In this work the stable control strategy during the low power operation and transient states is studied. To solve the problem, a fuzzy logic control method is applied as a basic algorithm of the controller. The control algorithm is based on the operator's knowledges and the experiences of manual operation for water level control at the compact nuclear simulator set up in Korea Atomic Energy Research Institute. From a viewpoint of the system realization, the control variables and rules are established considering simpler tuning and the input-output relation. The control strategy includes the dynamic tuning method and employs a substitutional information using the bypass valve opening instead of incorrectly measured signal at the low flow rate as the fuzzy variable of the flow rate during the pressure control mode of the steam generator. It also involves the switching algorithm between the control valves to suppress the perturbation of water level. The simulation results show that both of the fine control action at the small level error and the quick response at the large level error can be obtained and that the performance of the controller is improved.

• Journal of Korean Society of Transportation
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• v.24 no.1 s.87
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• pp.73-84
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• 2006

This study was carried out to set up the logic to determine lengths of the homogeneous sections effectively in order to provide dynamic travel time on real time base for the application of the model. First, considering real time traffic pattern fluctuation, lengths of the homogeneous sections for each time period and the final homogeneous sections were determined. In order to determine lengths of the homogeneous sections according to traffic condition, the cluster analysis was used based on real time data. In order to verify the homogeneous section the case with detectors in all links and the case with detectors in homogeneous section for each time period are used. As the results of verification, each cases showed similar estimation results. The results of this study are expected to be used for National Highway traffic management and the system to Provide a traffic information in the future. According to this study, when the homogeneous section decision model are used to the ITS project for National Highway, operation cost is expected to be cut by effectively establishing point detectors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.27-38
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• 2016

This work proposes a 12b 30MS/s 0.18um CMOS SAR ADC based on low-power composite switching with an active die area of $0.16mm^2$. The proposed composite switching employs the conventional $V_{CM}$-based switching and monotonic switching sequences while minimizing the switching power consumption of a DAC and the dynamic offset to constrain a linearity of the SAR ADC. Two equally-divided capacitors topology and the reference scaling are employed to implement the $V_{CM}$-based switching effectively and match an input signal range with a reference voltage range in the proposed C-R hybrid DAC. The techniques also simplify the overall circuits and reduce the total number of unit capacitors up to 64 in the fully differential version of the prototype 12b ADC. Meanwhile, the SAR logic block of the proposed SAR ADC employs a simple latch-type register rather than a D flip-flop-based register not only to improve the speed and stability of the SAR operation but also to reduce the area and power consumption by driving reference switches in the DAC directly without any decoder. The measured DNL and INL of the prototype ADC in a 0.18um CMOS are within 0.85LSB and 2.53LSB, respectively. The ADC shows a maximum SNDR of a 59.33dB and a maximum SFDR of 69.83dB at 30MS/s. The ADC consumes 2.25mW at a 1.8V supply voltage.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.251-258
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• 2012

Recently, NAND Flash memory structure is evolving from SDR (Single Data Rate) to high speed DDR(Double Data Rate) to fulfill the high performance requirement of SSD and SSS. Accordingly, the proper ways of transferring data that latches valid data stably and minimizing data skew between pins by using PHY(Physical layer) circuit techniques have became new issues. Also, rapid growth of speed in NAND flash increases the operating frequency and power consumption of NAND flash controller. Internal voltage variation margin of NAND flash controller will be narrowed through the smaller geometry and lower internal operating voltage below 1.5V. Therefore, the increase of power budge deviation limits the normal operation range of internal circuit. Affection of OCV(On Chip Variation) deteriorates the voltage variation problem and thus causes internal logic errors. In this case, it is too hard to debug, because it is not functional faults. In this paper, we propose new architecture that maintains the valid timing window in cost effective way under sudden power fluctuation cases. Simulation results show that the proposed technique minimizes the data skew by 379% with reduced area by 20% compared to using PHY circuits.