• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.8
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• pp.851-856
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• 2010

This paper presents an efficiency enhancement for the balanced power amplifier using DBS(Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. In order to apply the dynamic biases to each side of the balanced power amplifier, two switching stages are adopted. Using an OFDM signal with a bandwidth of 20 MHz and a PAR(Peak to Average Ratio) of 8.5 dB, 6 % of PAE(Power-Added Efficiency) is improved at an output power of 42.5 dBm.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.317-320
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• 2000

In this paper, a 0.5W, 2GHz high-efficiency class A power amplifier using the dynamic bias control is proposed. First of all, the drain bias control amplifier is analyzed theoretically and designed with commercial devices. Simulation results show that the proposed amplifier has a significant improved efficiency, compared to fixed bias power amplifier.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.133-136
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• 2002

This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.

• Progress in Superconductivity
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• v.5 no.1
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• pp.31-37
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• 2003

Wide-bandwidth SQUID current amplifier and its control electronics have been constructed for detecting pulse outputs of a superconducting microcalorimeter. The current amplifier made of a double relaxation oscillation SQUID (DROS) has a bandwidth of 1.2 MHz and typical white noise level of about 6 pA/(equation omitted) Hz. To increase the dynamic range of the current amplifier, the flux-locked loop (FLL) has additional circuits to reset the integrator and to count reset numbers which present the number of passed flux quanta. In this system, dynamic range covers from -65 mA to +65 mA. SQUID electronics are controlled by software to get the optimum FLL condition, and to control the current to bias the transition edge sensor (TES). The electronics are shielded from the outside electromagnetic noises by using an aluminum case of 66 mm ${\times}$ 25 mm ${\times}$ 100 mm, and consist of 2 separate printed-circuit-boards for the current amplifier and the control electronics, respectively. The SQUID current amplifier and its control electronics will be used in TESs for detecting photons such as UV and X-ray with high energy resolution.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.73-81
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• 1994

It is AGC(Automatic Gain Control) amplifier to decide characteristics of IF(Intermediate Frequency) processing IC. When demodulated IF signal by PLL type demodulator, the amplitude of input singla should be maintained at a certain amplitude. The AGC amplifier is an important factor to achieve this condition. The AGC amplifier needs the wide dynamic range, the wide AGC range and better noise characteristics. We designed the AGC amplifier to satisfy these characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.8
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• pp.795-801
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• 2014

This paper presents an efficiency enhancement for the high power amplifier using DDBS(Digitally-controlled Dynamic Bias Switching) method which dynamically provides the power amplifier with two bias voltage levels according to the input envelope signal. It is quite easy to adjust the control signal by using a digital processing. The fabricated DDBS PA was evaluated using an 64 QAM FDD LTE signal, which has a center frequency of 2.6 GHz, a bandwidth of 10 MHz and a PAPR of 9.5 dB. The DDBS increases the power amplifier's PAE(Power-Added Efficiency) from 40.9 % to 48 %, at an average output power level of 43 dBm.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.6 s.109
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• pp.538-545
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• 2006

In this paper, an asymmetric high power extended Doherty amplifier for WCDMA base-station applications is presented. The amplifier has an extended peak efficiency over 9 dB of output power and a linear dynamic range characteristic. To realize the peak efficiency extension and linear dynamic range characteristic, a two times larger peaking device compared to the main device, and an unequal power divider are used. From the experimental results of 1FA WCDMA signal, this amplifier has an efficiency of 31 % and an ACLR of -35 dBc is achieved at 9 dB back-off from P1 dB.

• Journal of Advanced Navigation Technology
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• v.3 no.1
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• pp.52-59
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• 1999

Digital microwave wideband receiver including linear amplifier, analog-to-digital converter(ADC) and digital signal processor is able to analyze its performance using sensitivity and dynamic range of system. Determination of gain, third-order intermodulation products and ADC characteristics and design criteria for the linear amplifier chain is essential problem for sensitive and dynamic range. Also, if there are two signals with frequencies very close, digital signal processor must be able to separate the two signals. In this paper, we measured dynamic range as gain was changed and determined gain value for the proper sensitivity and dynamic range and high resolution spectrum estimation was used to separate two close signals.