• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.11B
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• pp.1631-1639
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• 2010

This paper proposes a scheduling algorithm that can reduce the power consumed for execution of application programs and the communication cost incurred due to dependencies among tasks. The proposed scheduling algorithm can increase energy efficiency of the DVS(Dynamic Voltage Scaling) by estimating laxity usage during scheduling, making up for conventional algorithms that apply the DVS after scheduling. Energy efficiency can be increased by applying the proposed algorithm to complex multimedia applications. Experimental results show that energy consumptions for executing HD MPEG4, MotionJPEG codec, MP3, and Wavelet have been reduced by 11.2% on the average, when compared to conventional algorithms.

• Journal of the Korea Society of Computer and Information
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• v.16 no.6
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• pp.11-20
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• 2011

In this paper, we propose an optimal scheduling scheme that minimizes the energy consumption of a real-time video task on the multi-core platform supporting dynamic voltage and frequency scaling. Exploiting parallel execution on multiple cores for less energy consumption, the propose scheme allocates an appropriate number of cores to the task execution, turns off the power of unused cores, and assigns the lowest clock frequency meeting the deadline. Our experiments show that the proposed scheme saves a significant amount of energy, up to 67% and 89% of energy consumed by two previous methods that execute the task on a single core and on all cores respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.304-308
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• 2009

This paper presents the deadline driven CPU-Power management scheme for the Real-Time Embedded OS: named TMO-eCos. It used the scheduling scenarios generated by a task serialization technique for hard real- time TMO system. The serializer does a off-line analysis at design time with period, deadline and WCET of periodic tasks. Finally, TMO-eCos kernel controls the CPU speed to save the power consumption under the condition that periodic tasks do not violate deadlines. As a result, the system shows a reasonable amount of power saving. This paper presents all of these processes and test results.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.517-526
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• 2008

As the functionality of portable devices arc being enhanced and the performance is being greatly improved, power dissipations of battery driven portable devices are being increased. So, an efficient power management for reducing their power consumption is needed. In this paper, we propose a window-based DVS algorithm for MPEG Player. The proposed algorithm maintains the recently frame information and execution time received from MPEG player in window queue and dynamically adjusts (frequency, voltage) level based on window queue information. Our algorithm can be implemented in the common multimedia player as a module. We employed well-known MPlayer for the measurement of performance. The experimental result shows that the proposed algorithm reduces energy consumption by 56% on maximal performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.135-140
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• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• Journal of IKEEE
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• v.15 no.4
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• pp.305-312
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• 2011

A primary interest of this work is to develop an efficient and powerful repetitive pulser system for the application of ultra wide band generation. The important component of the pulser system is a small-sized coaxial type spark gap with planar electrodes filled with SF6 gas. A repetitive switching action by the coaxial spark gap generates two consecutive pulses in less than a microsecond with rise times of a few hundred picoseconds (ps). A set of several parameters for the repetitive switching of the spark gap is required to be optimized in charging and discharging systems of the pulser. The parameters in the charging system include a circuit scheme, circuit elements, the applied voltage and current ratings from power supplies. The parameters in the discharging system include the spark gap geometry, electrode gap distance, gas type, gas pressure and the load. The characteristics of the spark gap discharge, such as breakdown voltage, output current pulse and recovery rate are too dynamic to control by switching continuously at a high pulse repetition rate (PRR). This leads to a low charging efficiency of the spark gap system. The breakthrough of the low charging efficiency is achieved by a parallel operation of two spark gaps system. The operational behavior of the two spark gaps system is presented in this paper. The work has focused on improvement of the charging efficiency by scaling the PRR of each spark gap in the two spark gaps system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.52-60
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• 2010

In this paper, we propose a dynamic power management framework for multi-core systems. We reduced the power consumption of multi-core processors such as Intel Centrino Duo and ARM11 MPCore, which have been used at the consumer electronics and personal computer market. Each processor uses a different technique to save its power usage, but there is no embedded multi-core processor which has a precise power control mechanism such as dynamic voltage scaling technique. The proposed dynamic power management framework is suitable for smart phones which have an operating system to provide multi-processing capability. Basically, our framework follows an intuitive idea that reducing the power consumption of idle cores is the most effective way to save the overall power consumption of a multi-core processor. We could minimize the energy consumption used by idle cores with application-targeted policies that reflect the characteristics of active workloads. We defined some properties of an application to analyze the performance requirement in real time and automated the management process to verify the result quickly. We tested the proposed framework with popular processors such as Intel Centrino Duo and ARM11 MPCore, and were able to find that our framework dynamically reduced the power consumption of multi-core processors and satisfied the performance requirement of each program.

• KIISE Transactions on Computing Practices
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• v.20 no.11
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• pp.604-609
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• 2014

Decoding processes in portable media players have a high computational cost, resulting in high power consumption by the CPU. If decoding computations are reduced, the power consumed by the CPU is also be reduced, but such a choice generally results in a degradation of the video quality for the users, so it is essential to address this tradeoff. We proposed a new CPU power management scheme that can make use of the scalability property available in the H.164/SVC standard. We first proposed a new video quality model that makes use of a video quality metric(VQM) in order to efficiently take into account the different quantization factors in the SVC. We then propose a new dynamic voltage scaling(DVS) scheme that can selectively combine the previous decoding times and frame sizes in order to accurately predict the next decoding time. We then implemented a scheme on a commercial smartphone and performed a user test in order to examine how users react to the VQM difference. Real measurements show that the proposed scheme uses up to 34% fewer energy than the Linux DVFS governor, and user tests confirm that the degradation in the quality is quite tolerable.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1423-1435
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• 2010

Building wireless sensor networks requires a constituting sensor node to consider the following limited hardware resources: a small battery lifetime limiting available power supply for the sensor node, a low-power microprocessor with a low-performance computing capability, and scarce memory resources. Despite such limited hardware resources of the sensor node, the sensor node platform needs to activate real-time sensing, guarantee the real-time processing of sensing data, and exchange data between individual sensor nodes concurrently. Therefore, in this paper, we propose an energy-efficient real-time task scheduling technique for battery-powered wireless sensor nodes. The proposed energy-efficient task scheduling technique controls the microprocessor's operating frequency and reduces the power consumption of a task by exploiting the slack time of the task when the actual execution time of the task can be less than its worst case execution time. The outcomes from experiments showed that the proposed scheduling technique yielded efficient performance in terms of guaranteeing the completion of real-time tasks within their deadlines and aiming to provide low power consumption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.8
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• pp.2821-2839
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• 2015

Energy consumption by large computing systems has become an important research theme not only because the sources of energy are depleting fast but also due to the environmental concern. Computational grid is a huge distributed computing platform for the applications that require high end computing resources and consume enormous energy to facilitate execution of jobs. The organizations which are offering services for high end computation, are more cautious about energy consumption and taking utmost steps for saving energy. Therefore, this paper proposes a scheduling technique for Minimizing Energy consumption using Adapted Genetic Algorithm (MiE-AGA) for dependent tasks in Computational Grid (CG). In MiE-AGA, fitness function formulation for energy consumption has been mathematically formulated. An adapted genetic algorithm has been developed for minimizing energy consumption with appropriate modifications in each components of original genetic algorithm such as representation of chromosome, crossover, mutation and inversion operations. Pseudo code for MiE-AGA and its components has been developed with appropriate examples. MiE-AGA is simulated using Java based programs integrated with GridSim. Analysis of simulation results in terms of energy consumption, makespan and average utilization of resources clearly reveals that MiE-AGA effectively optimizes energy, makespan and average utilization of resources in CG. Comparative analysis of the optimization performance between MiE-AGA and the state-of-the-arts algorithms: EAMM, HEFT, Min-Min and Max-Min shows the effectiveness of the model.