• Title/Summary/Keyword: Dual-frequency modulation

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Design of a CCM/DCM dual mode DC-DC Buck Converter with Capacitor Multiplier (커패시터 멀티플라이어를 갖는 CCM/DCM 이중모드 DC-DC 벅 컨버터의 설계)

  • Choi, Jin-Woong;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.9
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    • pp.21-26
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    • 2016
  • This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

THE MEASUREMENT OF THE IONOSPHERIC TOTAL ELECTRON CONTENT USING P-CODE OF GPS (GPS의 P 코드를 이용한 이온층의 총전자수 측정)

  • 서윤경;박필호;박종욱;이동훈
    • Journal of Astronomy and Space Sciences
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    • v.11 no.1
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    • pp.71-80
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    • 1994
  • It is generally known that the measurement of the ionospheric total electron content(TEC) by GPS can more accurately monitor the broader area of the ionosphere than other current methods. \Ve measured the TEC along a slant path considering the arrival time differences of P-code which is transmitted from GPS satellites with the modulation on two L-band carrier frequencies, L1 (1574.42MHz) and L2 (1227.60MHz). Under the assumptions that the ionosphere is uniformly distributed and its average height is 350km, we transformed the slant TEC to the vertical TEC at the point that the line-of-sight direction to GPS satellite cut across the average height of the ionosphere. Because there is no dual frequency P-code GPS receiver in Korea, we used the data observed at the TAIW GPS station ($N25^{\circ},E121.5^{\circ}$) in Taiwan which is one of the core stations in International GPS and Geodynamics Services (IGS). The TEC values obtained in this work showed a typical daily variation of the ionosphere which is high in the daytime and low in the nighttime. Our results are found to be consistent with the SOLAR-DAILY data of NOAA and the Klobuchar's model for the ionospheric correction of GPS. In addition, in the cornparision with SOLAR-DAILY data, we estimated the precision of our TEC measurement as 2 TEC.

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Dual Effect of $H_2O_2$ on the Regulation of Cholecystokinin-induced Amylase Release in Rat Pancreatic Acinar Cells

  • An, Jeong-Mi;Rhie, Jin-Hak;Seo, Jeong-Taeg
    • International Journal of Oral Biology
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    • v.31 no.4
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    • pp.127-133
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    • 2006
  • [ $H_2O_2$ ], a member of reactive oxygen species (ROS), is known to be involved in the mediation of physiological functions in a variety of cell types. However, little has been known about the physiological role of $H_2O_2$ in exocrine cells. Therefore, in the present study, the effect of $H_2O_2$ on cholecystokinin (CCK)-evoked $Ca^{2+}$ mobilization and amylase release was investigated in rat pancreatic acinar cells. Stimulation of the acinar cells with sulfated octapeptide form of CCK (CCK-8S) induced biphasic increase in amylase release. Addition of $30\;{\mu}M\;H_2O_2$ enhanced amylase release caused by 10 pM CCK-8S, but inhibited the amylase release induced by CCK-8S at concentrations higher than 100 pM. An ROS scavenger, $10\;{\mu}M$ Mn(III)tetrakis(4-benzoic acid)porphyrin chloride, increased amylase release caused by CCK-8S at concentrations higher than 100 pM, although lower concentrations of CCK-8S-induced amylase release was not affected. To examine whether the effect of $H_2O_2$ on CCK-8S-induced amylase release was exerted via modulation of intracellular $Ca^{2+}$ signaling, we measured the changes in intracellular $Ca^{2+}$ concentration $([Ca^{2+}]_i)$ in fura-2 loaded acinar cells. Although $30\;{\mu}M\;H_2O_2$ did not induce any increase in $[Ca^{2+}]_i$ by itself, it increased the frequency and amplitude of $[Ca^{2+}]_i$ oscillations caused by 10 pM CCK-8S. However, $30\;{\mu}M\;H_2O_2$ had little effect on 1 nM CCK-8S-induced increase in $[Ca^{2+}]_i$. ROS scavenger, 1 mM N-acetylcysteine, did not affect $[Ca^{2+}]_i$ changes induced by 10 pM or 1 nM CCK-8S. Therefore, it was concluded that $30\;{\mu}M\;H_2O_2$ enhanced low concentration of CCK-8S-induced amylase release probably by increasing $[Ca^{2+}]_i$ oscillations while it inhibited high concentration of CCK-8S-induced amylase release.

A Design of PLL and Spread Spectrum Clock Generator for 2.7Gbps/1.62Gbps DisplayPort Transmitter (2.7Gbps/1.62Gbps DisplayPort 송신기용 PLL 및 확산대역 클록 발생기의 설계)

  • Kim, Young-Shin;Kim, Seong-Geun;Pu, Young-Gun;Hur, Jeong;Lee, Kang-Yoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.21-31
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    • 2010
  • This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.