• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.131-139
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• 2008

This paper presents a scalable dual-field Montgomery multiplier based on a new multi-precision carry save adder(MP-CSA), which operates in both types of finite fields GF(p) and GF($2^m$). The new MP-CSA consists of two carry save adders(CSA). Each CSA is composed of n = [w/b] carry propagation adders(CPA) for a modular multiplication with w-bit words, where b is the number of dual field adders(DFA) in a CPA. The proposed Montgomery multiplier has roughly the same timing complexity compared with the previous result, however, it has the advantage of reduced chip area requirements. In addition, the proposed circuit produces the exact modular multiplication result at the end of operation unlike the previous architecture. Furthermore, the proposed Montgomery multiplier has a high scalability in terms of w and m. Therefore, it can be used to multiplier over GF(p) and GF($2^m$) for cryptographic applications.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.11
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• pp.1117-1123
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• 2008

This paper implements dual-kernel system using standard Linux and real-time embedded Linux for the real-time control of intelligent robot systems. Such system provides more useful services including standard Linux thread that is easy to implement complicated tasks and real-time tasks for the deterministic response to velocity control. Here, an open source real-time embedded Linux, XENOMAI, is ported on embedded target board. And for interfacing with motor controller we adopted a real-time serial device driver. The real-time task was implemented with a priority to keep the cyclic control command for trajectory control. In order to validate deterministic response of the proposed system, the performance measurement of the delay in performing trajectory control with feedback loop is evaluated with non real-time standard Linux. The proposed software architecture is anticipated to take advantage of features in both standard Linux and real-time operating systems for the intelligent robot systems.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Journal of Positioning, Navigation, and Timing
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• v.11 no.4
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• pp.269-277
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• 2022

In this paper, we overview the system development status of the national maritime precise point positioning-real-time kinematic (PPP-RTK) service in Korea, also known as the Precise POsitioning and INTegrity monitoring (POINT) system. The development of the POINT service began in 2020, and the open service is scheduled to start in 2025. The architecture of the POINT system is composed of three provider-side facilities-a reference station, monitoring station, and central control station-and one user-side receiver platform. Here, we propose the detailed functionality of each component considering unidirectional broadcasting of augmentation data. To meet the centimeter-level user positioning accuracy in maritime coverage, new reference stations were installed. Each reference station operates with a dual receiver and dual antenna to reduce the risk of malfunctioning, which can deteriorate the availability of the POINT service. The initial experimental results of a testbed from corrections generated from the testbed network, including newly installed reference stations, are presented. The results show that the horizontal and vertical accuracies satisfy 2.63 cm and 5.77 cm, respectively. For the purpose of (near) real-time broadcasting of POINT correction data, we designed a correction message format including satellite orbit, satellite clock, satellite signal bias, ionospheric delay, tropospheric delay, and coordinate transformation parameters. The (near) real-time experimental setup utilizing (near) real-time processing of testbed network data and the designed message format are proposed for future testing and verification of the system.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.1
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• pp.1196-1204
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• 2001

In this paper, a new architecture of operating software associated with the component-based method is proposed. The proposed architecture comprises 문 execution module and a decision-making module. In order to make effective development and maintenance, the execution module is divided into three components. The components are referred to as Symbol, Gateway, and Control, respectively: The symbol component is for the GUI environments and the standard interfaces; the gateway component is for the network communication and the structure of asynchronous processes; the control component is for the asynchronous processing and machine setting or operations. In order to verify the proposed architecture, and off-line version of operating software is made, and its steps are as follows; I) Make virtual execution modules for the manufacturing devices such as dual-arm robot, handling robot, CNC, and sensor; ii) Make decision-making module; iii) Integrate the modules and GUI using a well-known development tools such as Microsofts Visual Basic; iv) Execute the overall operating software to validate the proposed architecture. The proposed software architecture in this paper has the advantages such as independent development of each module, easy development of network communication, and distributed processing of resources, and so on.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.23-30
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• 2006

This paper presents design andd verification of a circuit that improves the control-operation problems of Stored Program Optical Computer (SPOC), which is an optical computer using $LiNbO_3$ optical switching element. Since the memory of SPOC takes the Delay Line Memory (DLM) architecture and instructions that are needless of operands should go though memory access stages, SPOC memory have problems; it takes immoderate access time and unnecessary operations are executed in Arithmetic Logical Unit (ALU) because desired operations can't be selectively executed. In this paper, improvement on circuit has been achieved by removing the memory access of instructions that are needless of operands by decoding instructions before locating operand. Unnecessary operations have been reduced by sending operands to some specific operational units, not to all the operational units in ALD. We show that total execution time of a program is minimized by using the Dual Instruction Register(DIR) architecture.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.5
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• pp.949-958
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• 2018

A voice recognition control system is a system for controlling a peripheral device by recognizing a voice. Recently, a voice recognition control system have been applied not only to smart devices but also to various environments ranging from IoT(: Internet of Things), robots, and vehicles. In such a voice recognition control system, the recognition rate is lowered due to the ambient noise in addition to the voice of the user. In this paper, we propose a dual channel acoustic beamforming hardware architecture for MEMS(: Microelectromechanical Systems) microphones to eliminate ambient noise in addition to user's voice. And the proposed hardware architecture is designed as ASIC(: Application-Specific Integrated Circuit) using TowerJazz $0.18{\mu}m$ CMOS(: Complementary Metal-Oxide Semiconductor) technology. The designed dual channel acoustic beamforming ASIC has a die size of $48mm^2$, and the directivity index of the user's voice were measured to be 4.233㏈.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• Journal of architectural history
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• v.7 no.3 s.16
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• pp.87-105
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• 1998

Surveying the literature of architecture since the nineteenth century, one can identify two dominant but problematic attitudes, among several, that pursue the task of defining what modern architecture is and should be. The first is the search for meaning and the second is the pursuit of form. This study, following Michel Foucault, asserts that the dual formation of meaning and form is a historical product of modernity and belies architecture's uncritical dependence on language since the nineteenth century. This study is a critique and historical analysis of this pernicious reliance, and constitutes a first step towards thinking of alternative relations between 'words and architecture' in the modern world. In reconstructing this problematic, the paper has called on Foucault's seminal The Order of Things. The study follows his construction of the Renaissance, the Classical and the Modern episteme, and in brief fashion, reconstructs the relation between language and architecture in each episteme. In analysing the Modern, the study focuses on Hegel's Lectures on Aesthetics. Hegel placed architecture in a genre hierarchy within which architecture, because of its material basis, was fundamentally limited in its ability to express the Spirit. For Hegel it was, among the arts, poetic language, and beyond art, the language of philosophy, through which the Absolute Spirit could be atttained. Much of post-nineteenth century architecture has remained within the shadow of Hegel, where architecture's materiality is perceived to be a burden, and in order to secure its relevance in modern society, architecture was deemed to pursue the role of language. As the most recent and sophisticated example of architecture's pursuit of form, the paper analyses the work of Peter Eisenman. Though Eisenman's theoretical writings are replete with post-Hegelian rhetoric, his architecture remains dependent upon the model of language, albeit a structuralist one. The paper concludes that ultimately, the pursuit of meaning and form is unable to face the crucial issue of value in modernity. While the former decides to easily what it is, the latter evades the issue itself. The second installment of this ongoing study will pursue a third possibility alluded to by Foucault, where language remains silent, pointing only to its 'ponderous' material existence.

• ETRI Journal
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• v.27 no.5
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• pp.533-538
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• 2005

We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.