• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.551-558
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• 2012

This paper presents a dual band loop-type ground antenna using lumped-elements that control the impedance bandwidth and resonant frequency. The dual-band operation of the proposed antenna is realized by inserting an additional resonated loop feed structure into the reference ground antenna. As the proper value of the capacitor and the inductor are chosen, the impedance bandwidth of our antenna with voltage standing wave ratio(VSWR) equal to 3 is 85 MHz and 725 MHz at the 2.45 and 5.5 GHz frequency band, respectively. Its validity is demonstrated via both the computed and measured results. Good antenna patterns and efficiencies are achieved at the dual frequency bands, as well as the physically small antenna element size($10{\times}5mm^2$).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.11
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• pp.898-905
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• 2018

In this work, infrared targets for a developed hardware-in-the-loop simulation(HILS) system are proposed for a performance test of a dual-sensor imaging seeker equipped with an infrared and a visible sensor that can lock and track for ground and air targets. This integrated system is composed of 100 modules of heat and light sources to simulate various kinds of target and the trajectory of moving targets based on scenarios. It is possible to simulate not only the position, velocity, and direction for these targets but also background clutter and jamming environments. The design and measurement results of an infrared target, such as the HILS system configuration, developed for testing and evaluation of a dual-sensor imaging seeker are described. In the future, it is planned to test the lock-on and tracking performance of an imaging seeker equipped with single or dual sensors dynamically in real time based on a simulation flight scenario in the developed HILS system.

• Journal of the Korean Society for Precision Engineering
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• v.29 no.1
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• pp.79-86
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• 2012

This paper proposes PID and RIC (Robust Internal-loop Compensator) based motion controller using dual learning algorithm for position control of linear synchronous motor respectively. Its gains are auto-tuned by using two learning algorithms, reinforcement learning and neural network. The feedback controller gains are tuned by reinforcement learning, and then the feedforward controller gains are tuned by neural network. Experiments prove the validity of dual learning algorithm. The RIC controller has better performance than does the PID-feedforward controller in reducing tracking error and disturbance rejection. Neural network shows its ability to decrease tracking error and to reject disturbance in the stop range of the target position and home.

• Journal of Electrical Engineering and Technology
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• v.12 no.4
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• pp.1529-1536
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• 2017

A digital dual-channel interleaved phase-shift full-bridge converter is investigated in this paper, and its topology and principle are analyzed. To realize current sharing and stabilize the output voltage, a controller with current sharing loop and closed voltage loop is employed. In addition, current sharing will increase the output current fluctuation and a new digital interleaved driving technology is proposed to reduce the output current ripple. To verify the analysis, simulation and experiments are carried out, which shows the effectiveness of the proposed control strategies.

• ETRI Journal
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• v.31 no.4
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• pp.475-477
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• 2009

A balanced dual-band bandpass filter based on ${\lambda}$/2 stepped-impedance resonators and open-loop resonators is proposed in this letter. By employing a type of self-feedback structure, an extra transmission zero is introduced near the common-mode resonance frequency, and the common-mode signal is suppressed. The measured results indicate that the filter can operate in 2.46 GHz and 5.6 GHz bands, and the insertion loss is 1.85 dB and 1.9 dB, respectively. Also, better common-mode suppression is achieved.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1650-1660
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• 2016

This paper proposes a compensator to eliminate the DC bias of inductor current. This method utilizes an average-current sensing technique to detect the DC bias of inductor current. A small signal model of the DC bias compensation loop is derived. It is shown that the DC bias has a one-pole relationship with the duty cycle of the left side leading lag. By considering the pole produced by the dual active bridge (DAB) converter and the pole produced by the average-current sensing module, a one-pole-one-zero digital compensation method is given. By using this method, the DC bias is eliminated, and the stability of the compensation loop is ensured. The performance of the proposed compensator is verified with a 1.2-kW DAB converter prototype.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.465-470
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• 2010

The charge pump in a phase-locked loop is a key block in determining reference spurs of the VCO output signal. To reduce reference spurs, the current mismatch in the charge pump must be minimized. This paper presents a dual compensation method to reduce the current mismatch. The proposed charge pump and PLL were realized in a $0.18{\mu}m$ CMOS process. Measured current matching characteristics were achieved with less than 1.4% difference and with the current variation of 3.8% in the pump current over the charge pump output voltage range of 0.35-1.35V at 1.8V. The reference spur of the PLL based on the proposed charge pump was measured to be -71dBc.

• Transactions of the Korean Society of Automotive Engineers
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• v.20 no.2
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• pp.21-29
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• 2012

A dual loop waste heat recovery system with Rankine steam cycles for the improvement of fuel efficiency of gasoline vehicles has been investigated. A high temperature loop (HT loop) only recovers the heat of the exhaust gas. A low temperature loop (LT loop) recovers the residual heat from the HT loop, the coolant heat and the remaining exhaust gas heat. The two separate loops are coupled with a heat exchanger. This paper has dealt with a layout of the dual loop system, the review of the working fluids, and the design of the cycle. The design point and the target heat recovery of the HT boiler, a core part of a HT loop, have been presented. The prototype of the HT boiler was evaluated by experiment. For the performance evaluation of the HT boiler, inlet temperature of the HT boiler working fluid was set equal to the temperature degree of sub-cool of $5^{\circ}C$ at the condensing pressure. The exit condition was the degree of super-heat set at $5^{\circ}C$. The characteristics of the HT boiler such as heat recovery and pressure drops of fluids were evaluated with varying flow rates and inlet temperatures of exhaust gas under various evaporating pressure conditions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.62-64
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• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.