• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.475-485
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• 2010

This paper proposes a novel concept for a microstrip resonator that can function as a filter and as an antenna at the same time. The proposed structure consists of an outer ring, an open loop-type inner ring, a circular patch, and three ports. The frequencies where the proposed structure works as a filter and as an antenna, respectively, are determined primarily by the radius of the inner ring and the circular patch. The measured results show that, when the microstrip resonator operates as a filtering device, this filter has about 15.1 % bandwidth at the center frequency of 0.63 GHz and a minimum insertion loss of 1.5 dB within passband. There are three transmission zeros at 0.52 GHz, 1.14 GHz, and 2.22 GHz. In the upper stopband, cross coupling - taking place at the stub of the outer ring - and the open loop-type inner ring produce one transmission zero each. The circular patch generates the dual-mode property of the filter and another transmission zero, whose location can be easily adjusted by altering the size of the circular patch. The proposed structure works as an antenna at 2.7 GHz, showing a gain of 3.8 dBi. Compared to a conventional patch antenna, the proposed structure has a similar antenna gain. At the resonant frequencies of the filter and the antenna, high isolation(less than -25 dB) between the filter port and the antenna port can be obtained.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.150-157
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• 2021

Nowadays, a DC microgrid that can link various distributed power sources is gaining much attention. Accordingly, research on fault situations, such as line-to-line and line-to-ground faults of the DC microgrid, has been conducted to improve grid reliability. However, the blackout of an AC system and the oscillation of a DC bus voltage have not been reported or have not been sufficiently verified by previous research. In this study, a 20 kW DC microgrid testbed using a power HIL simulation technique is proposed. This testbed can simulate various fault conditions without any additional grid facilities and dangerous experiments. It includes the blackout of the DC microgrid caused by the AC utility grid's blackout, a drastic load increment, and the DC bus voltage oscillation caused by the LCL filter of the voltage source converter. The effectiveness of the proposed testbed is verified by using Opal-RT's OP5707 real-time simulator with a 3 kW prototype three-port dual-active-bridge converter.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.1
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• pp.113-120
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• 2014

In this paper, I present a new echo canceller using the adaptive cascade system identification (CSI) method, which a system response is divided into several responses so that each response is adaptively estimated and combined. Echo cancellation is required for a dual-duplex DSL, in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. Especially, for a fickle response, if the response is estimated by an adaptive filter, the filter needs more taps and the performance is decreased. But the response is divided into several responses, the computation complexities are decreased and the performance is increased. For the stage constant n, which represents the number of stages, if the response is not divided (n=1), the computation complexity of multiply is $2N^2$. And if the response is divided into two responses (n=2), the computation complexity of multiply is $2N^2$. Also, if n=3, the computation complexity is ${\frac{2}{3}}N^2$. Therefore, it is known that the computation complexity is decreased as n is increased. Finally, this proposed method is verified through simulation of echo canceller for digital subscriber line (DSL) application.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.10a
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• pp.183-187
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• 2008

This paper describes a power control scheme to improve the performance of a fuel cell battery hybrid power source for residential application. The proposed power control scheme includes a power control strategy to control the power flow of the fuel cell hybrid power system and a digital control technique for a front-end dc-dc converter of the fuel cell. The power control strategy enables the fuel cell to operate within the high efficiency region defined by the polarization curve and efficiency curve of the fuel cell. A dual boost converter with digital control is applied as a front-end dc-dc converter to control the fuel cell output power. The digital control technique of the converter employs a moving-average digital filter into its voltage feedback loop to cancel the low frequency harmonic current drawn from the fuel cell and then limits the fuel cell output current to a current limit using a predictive current limiter to keep the fuel cell operation within the high efficiency region as well as to minimize the fuel cell oxygen starvation.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.115-122
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• 1996

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.131-136
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• 2008

System을 통해 출력되는 신호를 측정할 때 정확한 측정을 방해하는 요소로 잡음이 있다. 이런 신호 측정의 방해 요소인 잡음을 제거 하는 방법 중의 하나로 Lock-in Amp(LIA)가 사용되고 있다. 본 논문에서는 잡음 신호의 제거를 위해 사용 하는 LIA를 제작 하고 특성을 파악 하였으며 RF통신을 이용하여 무선 형태로 제작 하였다. 현재 상용화된 LIA는 프로브를 통한 유선으로 측정신호의 입력을 받게 되지만 본 논문에서 제작된 LIA는 무선신호 형태로 입력 하게 된다. RF통신의 케리어 주파수는 447.9[MHz]로 Digital GMSK 변복조방식을 이용하였다. LIA의 제작은 Dual Phase Sensitive Detecter을 사용하였으며, 주요 구성 요소인 Phase Locked Loop, Phase Shifter, Phase Sensitive Detector, Low Pass Filter등의 구조와 특성을 조사하였다.

• Journal of Positioning, Navigation, and Timing
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• v.6 no.4
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• pp.195-203
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• 2017

A 2U cube satellite called SNUGLITE has been developed by GNSS Research Laboratory in Seoul National University. Its main mission is to perform actual operation by mounting dual-frequency global positioning system (GPS) receivers. Its scientific mission aims to observe space environments and collect data. It is essential for a cube satellite to control an Earth-oriented attitude for reliable and successful data transmission and reception. To this end, an attitude estimation and control algorithm, Attitude Determination and Control System (ADCS), has been implemented in the on-board computer (OBC) processor in real time. In this paper, the Extended Kalman Filter (EKF) was employed as the attitude estimation algorithm. For the attitude control technique, the Linear Quadratic Gaussian (LQG) was utilized. The algorithm was verified through the processor in the loop simulation (PILS) procedure. To validate the ADCS algorithm in the ground, the experimental verification via a single axis Hardware-in-the-loop simulation (HILS) was used due to the simplicity and cost effectiveness, rather than using the 3-axis HILS verification (Schwartz et al. 2003) with complex air-bearing mechanism design and high cost.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.6
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• pp.23-36
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• 2005

PLLs have been widely used for many applications including communication systems. This paper presents a VCO with an improved negative skewed delay scheme and a PLL using this VCO. The proposed VCO and PLL are intended for replacing traditional LC oscillators and PLLs used in communication systems and other applications. The circuit designs of the VCO and PLL are based on 0.18um CMOS technology with 1.8V supply voltage. The proposed VCO employs subfeedback loops using pass-transistors and needs two opposite control voltages for the pass transistors. The subfeedback loops speed up oscillation depending on the control voltages and thus provide a high oscillation frequency. The two voltage controls have opposite frequency gain characteristics and result in low phase-noise. The 7-stage VCO in 0.18um CMOS technology operates from $3.2GHz\~6.3GHz$ with phase noise of about -128.8 dBc/Hz at 1MHz frequency onset. For 1.8V supply voltage, the current consumption is about 3.8mA. The proposed PLL has dual loop-filters for the proposed VCO. The PLL is operated at 5GHz with 1.8V supply voltage. These results indicate that the proposed VCO can be used for radio frequency operations replacing LC oscillators. The circuits have been designed and simulated using 0.18um TSMC library.