• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.5
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• pp.2063-2081
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• 2018

A resource allocation algorithm is proposed in this paper to simultaneously minimize the total system power consumption and maximize the system throughput for the downlink of multi-user multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems. With the Lagrange dual decomposition method, we transform the original problem to its convex dual problem and prove that the duality gap between the two problems is zero, which means the optimal solution of the original problem can be obtained by solving its dual problem. Then, we use convex optimization method to solve the dual problem and utilize bisection method to obtain the optimal dual variable. The numerical results show that the proposed algorithm is superior to traditional single-objective optimization method in both the system throughput and the system energy consumption.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.14-22
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• 2023

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.11 s.102
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• pp.1106-1113
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• 2005

This paper presents a dual-band mixer for multi-standards of IEEE 802.1la/b/g using a single local oscillator, so as to improve the defects of legacy systems. Those systems have duplicate local oscillators and mixers to handle dual band signals, increasing complexity of system and power loss. The proposed circuit shows 11.6 dB, 16.8 dB of conversion loss and 8.77 dBm, 12.5 dBm of IIP3(Input 3rd Intercept Point) for respective bands when the two RF inputs of 2.452 and 5.260 GHz are down-converted to the identical 356 MHz If frequency. The RF-LO isolations are measured 36 dB, 41 dB at each frequencies and over 50 dB of LO-IF isolations are achieved at all cases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.13 no.12
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• pp.965-971
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• 2003

To reach high areal density, less track pitch is expected and more servo bandwidth is required. One approach to overcoming the problem is by using dual stage servo system. For this system. we have suggested new milliactuator based on the shear mode of piezoelectric elements to drive the head suspension assembly. In this paper, we introduce milliactuator and controller design method, PQ method. PQ method reduces the controller design problem for DISO (dual-input/single-output) systems to two standard controller design problems for SISO ( single-input/single-output) problems. The first part of PQ method directly addresses the issue of actuator output contribution, and the second part allows the use of traditional loop shaping to achieve the overall system performance. This paper shows how to employ the PQ method to meet aggressive close-loop performance specifications for a disk drive system with a VCM and piezoelectric milliactuator.

• Journal of Advanced Navigation Technology
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• v.14 no.6
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• pp.909-915
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• 2010

In this paper, the unequal power divider based on CRLH (Composite Right/Left-Handed) transmission line with dual-band characteristic is proposed. They consist of dual-band branch line hybrid coupler, the connection between input and isolation port of hybrid coupler and ${\lambda}/4$ impedance transformer. When the transmission line between input and isolation port of hybrid coupler is asymmetrical connected, the divider is obtained the output results of the equal phase and unequal power dividing ratio. The simulation results of the divider represent the power ratio of 0 dB ~ 20 dB. To validate a function of divider, the hybrid coupler and transformer with 880 MHz and 1850 MHz is implemented. As a result, the proposed unequal divider obtains the power ratio of 3.2 dB ~ 8.8 dB at 880 MHz and 2.5 dB ~ 14.0 dB at 1850 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• International Journal of Automotive Technology
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• v.8 no.6
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• pp.771-780
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• 2007

In recent studies, various types of multi mode electric variable transmissions of hybrid electric vehicles have been proposed. Multi mode electric variable transmission consists of two or more different types of planetary gear hybrid powertrain system(PGHP), which can change its power flow type by means of clutches for improving transmission efficiencies. Generally, the power flows can be classified into three different types such as input split, output split and compound split. In this study, we analyzed power transmission characteristics of the possible six input split systems, and found the suitable system for single or multi mode hybrid powertrain. The input split system used in PRIUS is identified as a best system for single mode, and moreover we identified some suitable systems for dual mode.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.746-755
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• 2014

In this paper, we propose the structure of a dual polarized system for a wireless communication. The proposed dual polarized antenna is formed by one vertical antenna and two horizontal antennas that are orthogonal to each other. Vertical and horizontal polarized antennas transmit different signals, but two orthogonal horizontal polarized antennas transmit the same data signals. So, the signals of the proposed dual polarized system construct two dual-polarization planes. And, only one dual-polarization plane with a large signal power is selected at the side of a receiver. The simulation results show that the proposed dual polarized system could obtain a higher capacity compared to an ordinary $2{\times}2$ MIMO (Multi-input Multi-output) system.