• 전력전자학회논문지
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• 제18권6호
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• pp.515-522
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• 2013

In this paper, a new PCS is proposed which is consisted of high boost dual converter and single phase half-bridge inverter. The proposed PCS is configured in parallel input / serial output, using two interleaved voltage doubler converter. Converter of the proposed PCS is distribute input current by configuring parallel input and reduced turn ratio of transformer by configuring serial output. Also, compositions of the inverter are composed of serial output capacitor of converter and half-bridge inverter. The dual converter and single phase half-bridge inverter is designed and characteristic of the new PCS is analysed. The system of the 1.5[kW] PCS is verified through an experimental about operation and stability.

• 한국통신학회논문지
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• 제42권4호
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• pp.864-870
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• 2017

본 논문은 넓은 부하 전류를 요구하는 휴대 기기에서 사용될 목적으로 주파수 전압 변환을 이용하여 모드 제어 가능한 듀얼 모드 벅 변환기를 설명한다. 기존의 히스테스테릭 벅 변환기의 문제인 저 부하에서의 PLL 보상 및 효율 저하를 제안하는 듀얼 벅 변환기의 개선된 PFM 모드를 통해 해결한다. 또한 기존의 듀얼 모드 벅 변환기의 주요 회로인 모드 제어기에서의 부하 변화 감지의 어려움과 느린 모드 전환 속도를 제안하는 모드 제어기로 개선 시킨다. 제안하는 모드 제어기는 최소 1.5us의 모드 전환 시간을 가진다. 제안하는 DC-DC 벅 변환기는 $0.18{\mu}m$ CMOS 공정에서 설계하였으며 칩 면적은 $1.38mm{\times}1.37mm$이다. 기생 소자를 포함한 인덕터와 커패시터를 고려한 후 모의실험 결과는 1~500mA의 부하 전류 범위에서 입력 전압을 2.7~3.3V를 가지며 PFM 모드는 65mV이내, 히스테리틱 모드에서는 고정된 스위칭 주파수 상태에서 16mV의 출력 리플 전압을 가지는 1.2V의 출력 전압을 생성한다. 제안하는 듀얼 모드 벅 변환기의 최대 효율은 80mA에서 95%를 나타내며 해당 전체 부하 범위에서 85% 이상의 효율을 지닌다.

• 전력전자학회논문지
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• 제13권6호
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• pp.453-460
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• 2008

본 논문은 중용량에 적합한 새로운 이중출력 LLC 공진형 DC/DC 컨버터에 관한 것으로써, 별도의 Post-regulator및 추가되는 제어 IC 없이 정밀한 이중출력이 가능한 새로운 방식의 컨버터를 제안한다. 제안된 컨버터의 제어방식은 펄스폭 변조(PWM)와 동시에 주파수 변조(PFM)를 통해 이루어지며 Master 와 Slave 출력을 각각 주파수, 듀티로 제어함으로써 Slave 출력을 위한 별도의 Post-Regulator 및 제어 IC가 필요 없기 때문에, 저가의 컨버터 구현이 가능하다. 또한 기존 LLC 공진형 DC/DC 컨버터와 같이 스위칭 소자의 영전압 스위칭이 보장되는 동시에, Post-Regulator 로 인한 손실이 없기 때문에 효율 및 발열 특성이 매우 우수하다. 본 논문에서는 제안된 컨버터의 우수성과 신뢰성 검증을 위해, 실제로 50" FHD급 PDP용 전원회로를 위한 시뮬레이션 검토 및 시작품을 제작하고 이를 이용한 실험결과를 바탕으로 제안된 컨버터의 타당성을 검증한다.

• 전력전자학회논문지
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• 제22권1호
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• pp.9-17
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• 2017

A parallel control algorithm of thyristor dual-converter power system for the DC power supply of railway is proposed. The circulating current and current imbalance generated during parallel operation can be limited to control the output voltage of each power system by using the proposed parallel control algorithm. The proposed control algorithm can also eliminate output current sensor to achieve the same output response without additional costs. The validity of the proposed algorithm is verified through simulation and experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.564-567
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• 1991

In this paper a predictive current control strategy is adopted in the D.C motor drive using dual converter. It is a kind of feedforward control working without overshoot within very short settling time. The difference to the well-known PI current control lies in considering the computer's ability of pre-calcurating the converter's behavior. By simulation it is shown that the predictive current control solve the problems of optimal PI current control, such as overshoot and settling time.

• Journal of Power Electronics
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• 제11권2호
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• pp.113-119
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• 2011

This paper presents a DSP based direct digital control design and implementation for a high power boost converter. A single loop and dual loop voltage control are digitally implemented and compared. The real time workshop (RTW) is used for automatic real-time code generation. Experimental results of a 20 kW boost converter based on the TMS320F2808 DSP during reference voltage changes, input voltage changes, and load disturbances are presented. The results show that the dual loop control achieves better steady state and transient performance than the single loop control. In addition, the experimental results validate the effectiveness of using the RTW for automatic code generation to speed up the system implementation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.195-197
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• 2001

This paper presents the circuit modeling and Control methods of PWM DC/DC Converter with Isolated dual outputs. The dual output converter topology is consisted of the two switch and single secondary winding. The control algorithm which is used by an adjusted PI control methods, of Dual Output PWM DC/DC converter is proposed in this paper. The proposed adjusted PI control method has faster response characteristics than conventional PI control methods at load change. The validity of the proposed adjusted control method is verified with the several interesting simulation results.

• 전기전자학회논문지
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• 제19권4호
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• pp.479-485
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• 2015

A resistance deviation-to-time interval converter based on dual-slope integration using second generation current conveyors (CCIIs) is designed for connecting resistive bridge sensors with a digital system. It consists of a differential integrator using CCIIs, a voltage comparator, and a digital control logic for controlling four analog switches. Experimental results exhibit that a conversion sensitivity amounts to $15.56{\mu}s/{\Omega}$ over the resistance deviation range of $0-200{\Omega}$ and its linearity error is less than ${\pm}0.02%$. Its temperature stability is less than $220ppm/^{\circ}C$ in the temperature range of $-25-85^{\circ}C$. Power dissipation of the converter is 60.2 mW.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3230-3232
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• 1999

In this paper describes the design and improvement of a hybrid module for dual slope A/D converter. Since the input voltage to be converted is very sensitive and small. A/D converter must have the temperature stability. low-drift, and the high-resolution the conversion. A dual slop A/D converter circuit which is controlled by microprocessoer has been developed to reduce the offset voltage and the drift characteristics of operation amplifiers, and to improve the A/D conversion speed. Also hybrid module has been adapted to obtain the to obtain the stable and accurate A/D conversion for low cost use. The evaluation of the designed hybrid module has been shown as having a good performance, which will give usefull application to the industrial measurements use.

• ETRI Journal
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• 제26권6호
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.