• Journal of IKEEE
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• v.19 no.4
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• pp.514-519
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• 2015

We propose the multiple gate structure of double gate junctionless metal oxide silicon field oxide transistor (JL MOSFET) for device optimization. Since different workfunction within multiple metal gates, electric potential nearby source and drain region is modulated in accordance with metal gate length. On current, off current and threshold voltage are influenced with gate structure and make possible to meet some device specification. Through the device simulation work, performance optimization of double gate JL MOSFETs are introduced and investigated.

• Proceedings of the KSR Conference
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• 2008.11b
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• pp.400-405
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• 2008

Motor is energy converting system to generate mechanical force from electrical power and there are various typed motors in home, office, factory, vehicles, aircraft, shipping, etc. Recently in compliance with performance and reliability and the applications of variable speed motors with invert driver are expanded. Almost high power inverter have IGBT and IGBT's fault cause motor system fault. If we can calculate and foresee troubles of IGBT, we can protect accident caused by motor system fault. In this paper, the deterioration test method of IGBT devices is proposed and the test results of proposed method are shown by evaluated equipment. The basic concept of proposed method is current-voltage characteristic curve test between drain and source of IGBT in open state. The applied voltage type is ramp and it is confirmed that the current-voltage curvet pattern of IGBT in open state represents IGBT's deterioration state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.572-578
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• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.12-18
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• 2008

Ag paste was employed for source and drain electrode of OTFTs and for the data metal lines of OTFT-OLED array on PC(polycarbonate) substrate. We tested two kinds of Ag-pastes such as pastes for 325 mesh and 500 mesh screen mask to examine the pattern ability and electrical performance for OTFTs. The minimum feature size was 60 ${\mu}m$ for 325 mesh screen mask and 40 ${\mu}m$ for 500 mesh screen mask. The conductivity was 60 $m{\Omega}/\square$ for 325 mesh and 133.1 $m{\Omega}/\square$ for 500 mesh. For the OTFT performance the mobility was 0.35 $cm^2/V{\cdot}sec$ and 0.12 $cm^2/V{\cdot}sec$, threshold voltage was -4.7 V and 0.9 V, respectively, and on/off current ratio was ${\sim}10^5$, for both screen masks. We applied the 500 mash Ag paste to OTFT-OLED array because of its good patterning property. The pixel was composed of two OTFTs and one capacitor and one OLED in the area of $2mm{\times}2mm$. The panel successfully worked in active mode operation even though there were a few bad pixels.

• Proceedings of the Korean Nuclear Society Conference
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• 2004.10a
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• pp.719-720
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• 2004

A multi-megawatt long pulse ion source (LPIS) of neutral beam injector was developed for the KSTAR. Beam extraction experiments of the LPIS were carried out at the neutral beam test stand (NBTS). Design requirements for the ion source were 120 kV/65 A deuterium beam and a 300 s pulse length. A maximum ion density of $9.1310^{11}$ $cm^{-3}$ was measured by using electric probes, and an optimum arc efficiency of 0.46 A/kW was estimated with ion saturation current of the probes, arc power, and total beam area. An arcing problem, caused by the structural defect of decelerating grid supporter, in the third gap was solved by the blocking of backstream ion particles, originated from the plasma in the neutralizer duct, through the unnecessary spaces on the side of grid supporter. A maximum drain power of 1.5 MW (i.e. 70 kV/21 A) with hydrogen was measured for a pulse duration of 0.5 s. Optimum beam perveance was ranged from 0.75 to 0.85. An improved design of accelerator for the effective control of beam particle trajectory should provide higher beam perveance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.66-74
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• 2012

In this paper, the impact of segregation layer density ($N_{DSL}$) and length ($L_{DSL}$) on scalability and analog/RF performance of dopant-segregated Schottky barrier (DSSB) SOI MOSFET has been investigated in sub-30 nm regime. It has been found that, although by increasing the $N_{DSL}$ the increased off-state leakage, short-channel effects and the parasitic capacitances limits the scalability, the reduced Schottky barrier width at source-to-channel interface improves the analog/RF figures of merit of this device. Moreover, although by reducing the $L_{DSL}$ the increased voltage drop across the underlap length reduces the drive current, the increased effective channel length improves the scalability of this device. Further, the gain-bandwidth product in a common-source amplifier based on optimized DSSB SOI MOSFET has improved by ~40% over an amplifier based on raised source/drain ultrathin-body SOI MOSFET. Thus, optimizing $N_{DSL}$ and $L_{DSL}$ of DSSB SOI MOSFET makes it a suitable candidate for future nanoscale analog/RF circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.57-63
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• 2008

In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio ($\tau_{sat}$) and increase of the thermal injection velocity ($V_{inj}$) contribute the increase of mobility. It is also shown that the decrease of the $\tau_{sat}$ is due to the decrease of the mean free path ($\lambda_O$). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased $V_{inj}$ because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.682-687
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• 2014

We have performed reverse gate bias stress tests on AlGaN/GaN-on-Si Heterostructure FETs (HFETs). The shift of threshold voltage ($V_{th}$) and the reduction of on-current were observed from the stressed devices. These changes of the device parameters were not permanent. We investigated the temporary behavior of the stressed devices by analyzing the temperature dependence of the instabilities and TCAD simulation. As the baseline temperature of the electrical stress tests increased, the changes of the $V_{th}$ and the on-current were decreased. The on-current reduction was caused by the positive shift of the $V_{th}$ and the increased resistance of the gate-to-source and the gate-to-drain access region. Our experimental results suggest that electron-trapping effect into the shallow traps in devices is the main cause of observed instabilities.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.2
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• pp.251-258
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• 1994

To apply the Power MOSFET to the high powerd circuits, the parallel operation of the Power MOSFET must be considered because of their low power rating. This means, in practical applications, design methods for the parallel operations are required. However, it is very difficult to investigate the problem of parallel operations by directly changing the internal parameters of the MOSFET. Thus, in this paper, the effects of internal parameters for the parallel operation are investigated using SPICE program which is often used and known that the program is very reliable. The investigation results show that while the gate resistance and gate capacitances are the parameters which affect to the dynamic switching operations, the drain and source resistances are the parameters which affect to the steady-state current unbalances. Through this investigation, the design methods for the parallel operation of the MOSFET are suggested, which, in turn, contributes to the practical use of Power MOSFETs.