• Journal of information and communication convergence engineering
• /
• v.13 no.4
• /
• pp.257-263
• /
• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.

• Proceedings of the KIEE Conference
• /
• 1997.07d
• /
• pp.1630-1632
• /
• 1997

We have investigated activation phenomena of implanted ions on silicon wafers using microwave(2.45GHz). It is found that the higher concentration of impurities makes the better activation effects by microwave annealing. We have exposed poly-Si TFTs by microwave in order to anneal and improved the device performance. Microwave activates source/drain ions and lowers the contact resistance so that the current of the poly-Si TFTs increases. In addition, the leakage current of hydrogen passivated poly-Si TFTs is decreased after microwave annealing, due to the diffusion of hydrogen ions and curing the defects in the poly-Si active channel.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.5
• /
• pp.339-343
• /
• 1999

This paper reports the characteristics of poly-Si TFT unitary CMOS circuits fabricated with various techniques, in order to investigate the optimum process conditions. The active films were deposited by PECVD and LPCVD using $SiH_4\; and\; Si_2H_6$ as source gas, and annealed by SPC and ELA methods. The impurity doping of the oource and drain electrodes was performed by ion implantation and ion shower. In order to investigate the AC characteristics of the poly-Si TFTs processed with various methods, we have examined the current driving characteristics of the polt-Si TFT and the frequency characteristics of 23-stage CMOS ring oscillators. Ithas been observed that the circuits fabricated using $Si_2H_6$ with low-temperature process of ELA exhibit high switching speed and current driving performances, thus suitable for real application of large area electronics.

• Proceedings of the KIEE Conference
• /
• 2007.11a
• /
• pp.79-80
• /
• 2007

A high performance organic phototransistor with dynamic range of 120 dB is demonstrated by employing soluble pentacene as a photo-sensing layer. The organic phototransistor used suspended source/drain (SSD) electrode structure, which provides a dark current level of ${\sim}10^{-14}$ A at positive gate bias. Under a steady-state illumination, the organic phototransistor exhibited a current modulation of $10^6$ compared to dark to give a dynamic range of 120 dB. These results suggest that the organic phototransistor based on TIPS pentacene can be a new premising candidate for low-cost and high-performance photo-sensing element for digital imaging applications.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.2
• /
• pp.110-119
• /
• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of Semiconductor Engineering
• /
• v.3 no.2
• /
• pp.161-167
• /
• 2022

Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.169-181
• /
• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.10
• /
• pp.54-61
• /
• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.2
• /
• pp.104-110
• /
• 2008

In this paper we proposed a new source-drain structure for N-type MOSFET which can suppress the output resistance reduction of a device in saturation region due to soft break down leakage at high drain voltage when the gate is biased around relatively low voltage. When a device is generally used as a switch at high gate bias the current level is very important for the operation. but in electronic circuit like an amplifier we should mainly consider the output resistance for the stable voltage gain and the operation at low gate bias. Hence with T-SUPREM simulator we designed devices that operate at low gate bias and high gate bias respectively without a extra photo mask layer and ion-implantation steps. As a result the soft break down leakage due to impact ionization is reduced remarkably and the output resistance increases about 3 times in the device that operates at the low gate bias. Also it is expected that electronic circuit designers can easily design a circuit using the offered N-type MOSFET device with the better output resistance.

• Proceeding of EDISON Challenge
• /
• 2017.03a
• /
• pp.428-432
• /
• 2017

Silicon 기반 Metal-oxide-semiconductor field-effect transistor (MOSFET)의 크기가 감소함에 따라 silicon자체의 물성적 한계가 나타나고 있다. 이를 극복하고자 III-V 화합물 반도체가 채널소자로서 각광받고 있다. 본 연구에서는 III-V 화합물반도체 중 $In_xGa_{1-x}As$는 Indium 조성에 따른 전자구조 및 n-type MOSFET의 소자 특성을 본다. Indium의 조성이 증가함에 따라 subband의 개수와 간격이 증가하게 되어 Density of state가 감소하게 된다. 이로 인하여 Indium의 조성이 증가함에 따라 $In_xGa_{1-x}As$ 채널 MOSFET에서 상대적으로 Fermi level을 더 많이 상승시키게 되어 potential barrier를 얇아지게 만들며 또한 에너지에 따른 전류 밀도를 넓게 분포하도록 만든다. 이로 인하여 단채널에서는 In 조성이 증가함에 따라 direct source-to-drain tunnelling current이 증가하게 된다. 이로 인하여 In 조성의 증가에 따라 subthreshold swing과 ON-state current가 저하된다.