• Journal of the Korean Society of Combustion
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• v.5 no.1
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• pp.19-30
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• 2000

The characteristics of NOx emissions in pure hydrogen nonpremixed flames with coaxial air are analyzed numerically for the three model cases of coaxial air flames classified by varying coaxial air velocity and/or fuel velocity. In coaxial air flames, the flame length is reduced by coaxial air and can be represented as a function of the ratio of coaxial air to fuel velocity. Coaxial air decreases flame reaction zone, resulting in reducing flame residence time significantly. Finally, the large reduction of EINOx is achieved by the decrease of the flame residence time. It is found that because coaxial air can break down the flame self-similarity law, appropriate scaling parameters, which are different from those in the simple jet flames, are recommended. In coaxial air flames, the flame residence time based on the flame volume produces better results than that based on a cube of the flame length. And some portion of deviations from the 1/2 scaling law by coaxial air may be due to the violation of the linear relationship between the flame volume and the flame reaction zone.

• Proceedings of the Korean Radioactive Waste Society Conference
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• 2018.11a
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• pp.95-96
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• 2018

• ETRI Journal
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• v.36 no.1
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• Proceedings of the Korea Water Resources Association Conference
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• 2009.05a
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• pp.1250-1253
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• 2009

기후변화가 수자원에 미치는 영향을 평가하는데 있어서 주로 기후모형인 Global Climate Model (GCM)이 사용되고 있다. 그러나 이러한 기후모형의 공간적 해상도는 $3^{\circ}{\sim}4^{\circ}$ 정도로 한반도의 경우 바다로 묘사되기도 한다. 따라서 GCM을 이용해서 기후변화가 유역단위 수자원에 미치는 영향을 평가하기 위해서는 일반적으로 축소기법이 사용되고 있다. 현재까지 다양한 축소기법이 개발되었으며, 대표적인 모형으로는 SDSM(Statistical Down-Scaling Model)과 LARS-WG(The Long Ashton Research Station Weather Generator)이 있다. 이에 본 연구에서는 SDSM, LARS-WG와 함께 최근에 축소기법으로 사용되고 있는 인공신경망 기법을 이용해서 CCCMA(Canadian Centre for Climate Modeling and Analysis)에서 일 단위로 모의한 CGCM3 A2 시나리오를 기반으로 우포늪의 강우 및 온도시나리오를 구축하였다. 대상 지점인 우포늪은 경상남도 창녕군 우포늪(위도 $35^{\circ}$33', 경도 $128^{\circ}$25')에 위치하고 있으며, 모의 기간은 CASE1의 경우 현재, CASE2는 2050$^{\sim}$ 2080년, CASE3는 2080년$^{\sim}$2100년으로 각각 구분하여 축소기법을 적용하였다. 축소결과 축소기법에 따라 일정정도 차이를 보이기는 하였으나 강우와 온도 모두 증가하게 됨을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.11a
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• pp.145-150
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• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Proceedings of the Korea Water Resources Association Conference
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• 2020.06a
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• pp.249-249
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• 2020

수공구조물을 설계하기 위해서는 다양한 지속기간에 대한 설계수문량을 추정해야 한다. 국내의 경우도 기후변화로 인한 이상기후의 발생으로 1~2시간 동안 강우강도가 큰 집중호우가 발생하여 도시홍수를 발생시키며 직접 또는 간접적으로 피해를 주고 있다. 특히 북한 지역은 강우관측소가 존재하지 않은 지역이 많아 수공구조물 설계에 필요한 설계수문량을 추정하기에 많은 어려움이 있다. 본 연구에서는 하향스케일링(down-scaling)을 이용하여 북한 지역의 24시간 이내의 확률강우량을 추정하고자 한다. 이를 위하여 미계측 유역인 화천댐 상류유역의 지역빈도해석과 군집분석을 수행하여 수문학적 동질성을 확보하였고, 한강유역을 4개의 동질지역으로 구분하였다. 스케일 성질은 동일한 분포형을 가정하므로 수문학적 동질성이 확보된 기준 지속기간의 자료로부터 임의이 지속기간에 대한 확률강우량 추정이 가능하다. 따라서 북한지역의 짧은 지속기간에 대한 확률 강우량 추정을 위하여 동일한 지역 내의 지역 스케일 지수와 스케일 인자를 이용하여 하향스케일링을 적용할 수 있으며, 단기 혹은 장기에 해당하는 지속기간에 대한 확률강우량을 추정할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.309-324
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• 1987

In recent years has been an increasing interest with respect to using the discrete cosine transform(DCT) of which performance is found close to that of the Karhumen-Loeve transform, known to be optimal in the area of digital image processing for tha purpose of the image data compression. Among most of reported algorithms aimed at lowering the coputation complexity. Chen's algorithm is is found to be most popular, Recently, Lee proposed a now algorithm of which the computational complexity is lower than that of Chen's. but its performance is significantly degraded by FWL(Finite-Word-Lenght) effects as a result of employinga a fixed-poing arithmetic. In this paper performance evaluation of these two algorithms and error analysis of FWL effect are described. Also a scaling technique which we call Up & Down-scaling is proposed to allevaiate a performance degradation due to fixed-point arithmetic. When the 16x16point 2DCT is applied on image data and a 16-bit fixed-point arithmetic is employed, both the analysis and simulation show that is colse to that of Chen's.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.43-53
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• 2003

Unlike in analog display devices, the physical screen resolution in digital devices are fixed from the manufacturing. It is a weak point on digital devices. The screen resolution displayed in digital display devices is varied. Thus, interpolation or decimation of the resolution on the display is needed to make the input pixels equal to the screen resolution., This process is called image scaling. Many researches have been developed to reduce the hardware cost and distortion of the image of image scaling algorithm. In this paper, we proposed a Winscale algorithm. which modifies the scale up/down in continuous domain to the scale up/down in discrete domain. Thus, the algorithm is suitable to digital display devices. Hardware implementation of the image scaler is performed using Verilog XL and chip is fabricated in a 0.5${\mu}{\textrm}{m}$ Samsung SOG technology. The hardware costs as well as the scalabilities are compared with the conventional image scaling algorithms that are used in other software. This Winscale algorithm is proved more scalable than other image-scaling algorithm, which has similar H/W cost. This image-scaling algorithm can be used in various digital display devices that need image scaling process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.130-138
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• 2006

We have investigated pattern scaling down of silicon stamps through the oxidation technique, During oxidizing the silicon stamps, silicon dioxide that has 300 nm and 500 nm thickness was grown, and critical deformations were not observed in the patterns. There was positive effect to reduce size of patterns because vertical and horizontal patterns have different orientation. We achieved pattern reduction rate of $26\%$. In addition, the formation of polymer patterns had been investigated with varied temperature and pressure conditions to improve the filling characteristics of polymers during nanoimprint lithography when pattern sizes were few micrometers. In these varied conditions, polymers had been affected by free space compensation and elastic stress relaxation for filling the cavities. Based on the results, defect control which is an important issue in the nanoimprint lithography were facilitated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.