Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Improved Defect Control Problem using Scaled Down Silicon Oxide Stamps for Nanoimprint Lithography

나노임프린트 리소그래피를 위한 스케일 다운된 산화막 스탬프 제작과 패턴결함 개선에 관한 연구

  • Published : 2006.02.01
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Abstract

We have investigated pattern scaling down of silicon stamps through the oxidation technique, During oxidizing the silicon stamps, silicon dioxide that has 300 nm and 500 nm thickness was grown, and critical deformations were not observed in the patterns. There was positive effect to reduce size of patterns because vertical and horizontal patterns have different orientation. We achieved pattern reduction rate of $26\%$. In addition, the formation of polymer patterns had been investigated with varied temperature and pressure conditions to improve the filling characteristics of polymers during nanoimprint lithography when pattern sizes were few micrometers. In these varied conditions, polymers had been affected by free space compensation and elastic stress relaxation for filling the cavities. Based on the results, defect control which is an important issue in the nanoimprint lithography were facilitated.

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References

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