• Title/Summary/Keyword: Down-Mixer

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A 5.8GHz SiGe Down-Conversion Mixer with On-Chip Active Batons for DSRC Receiver (DSRC수신기를 위한 능동발룬 내장형 5.8GHz SiGe 하향믹서 설계 및 제작)

  • 이상흥;이자열;이승윤;박찬우;강진영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.4A
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    • pp.415-422
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    • 2004
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8 ${\mu}{\textrm}{m}$ SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm${\times}$1.3 mm and the measured performance was 7.5 ㏈ conversion gain, -2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.

60 GHz WPAN LNA and Mixer Using 90 nm CMOS Process (90 nm CMOS 공정을 이용한 60 GHz WPAN용 저잡음 증폭기와 하향 주파수 혼합기)

  • Kim, Bong-Su;Kang, Min-Soo;Byun, Woo-Jin;Kim, Kwang-Seon;Song, Myung-Sun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.1
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    • pp.29-36
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    • 2009
  • In this paper, the design and implementation of LNA and down-mixer using 90 nm CMOS process are presented for 60 GHz band WPAN receiver. In order to extract characteristics of the transistor used to design each elements under the optimum bias conditions, the S-parameter of the manufactured cascode topology was measured and the effect of the RF pad was removed. Measured results of 3-stages cascode type LNA the gain of 25 dB and noise figure of 7 dB. Balanced type down-mixer with a balun at LO input port shows the conversion gain of 12.5 dB within IF frequency($8.5{\sim}11.5\;GHz$) and input PldB of -7 dBm. The size and power consumption of LNA and down-mixer are $0.8{\times}0.6\;mm^2$, 43 mW and $0.85{\times}0.85\;mm^2$, 1.2 mW, respectively.

0.18mm CMOS LNA/Mixer for UHF RFID Reader (UHF RFID 리더를 위한 0.18mm CMOS LNA/Mixer)

  • Woo, Jung-Hoon;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.2
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    • pp.45-49
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    • 2009
  • In this paper, a direct down conversion LNA/Mixer has been designed and tested for 900Mhz UHF RFID application. The designed circuit has been implemented in 0.18um CMOS technology with 3.3V operation. In this work, a common gate input architecture has been used to cope with the higher input self jamming level. This LNA/Mixer is designed to support two operating modes of high gain mode and low gain mode according to the input jamming levels. The measured results show that the input referred P1dBs are 4dBm of high gain mode and 11dBm of low gain mode, and the conversion gains are 12dB and 3dB in high and low gain mode respectively The power consumptions are 60mW for high gain mode and 79mW for low gain mode. The noise figures are 16dB and 20dB in high gain mode and low gain mode respectively.

Design and Fabrication of 2 GHz Double Balanced Star Mixer Using a Novel Balun (새로운 발룬 회로를 이용한 2 GHz 대역 이중 평형 Star 혼합기의 설계 및 제작)

  • Kim, Sun-Sook
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2003.11a
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    • pp.630-637
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    • 2003
  • In this paper, a DBM(double balanced mixer) of 2 GHz is implemented on FR4(h=1.6mm, ${\epsilon}_r=4.6$) substrate. The structure of double balanced mixer requires, in general, two talons and a quad diode. For balun, a novel planar balun using microstrip to CPS(Coplanar Strip) is suggested and designed. The suggested balun shows the phase imbalance of $180^{\circ}{\pm}1.5^{\circ}$ and the amplitude imbalance of ${\pm}0.2 dB$ for 1.5 to 2.5 GHz. Using the balun, DBM is successfully implemented, and the measured conversion loss of up/down converter show about 6 dB over the bandwidth. The balun may be applicable for MMIC(Monolithic Microwave Integrated Circuit) DBM with the process supporting backside via though more study.

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A Study for active MMIC (능동 MMIC mixer에 관한 연구)

  • Kim, Young-Gi;Baek, Kyoung-Sik;Kim, Hyuk;Yoon, Shin-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.12
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    • pp.14-24
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    • 2001
  • An active MMIC L-band down converting mixer was designed by using GaAs FET with 0.5 ${\mu}$m gate length and 300 ${\mu}$m gate width. Main circuit topology was cascoded two active FETs. It consumed only 7.5 mA with 3V DC voltage supply. Conversion gain of 6.63 dB, minumium noise figure of 5.06 dB and Input $3^{rd}$ Order Intercept Point of 6.4 dBm were obtained. The chip size is 1.86 mm ${\times}$ 1.28 mm.

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Design and Fabrication of RF evaluation board for 900MHz (900MHz대역 수신기용 RF 특성평가보드의 설계 및 제작)

  • 이규복;박현식
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.3
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    • pp.1-7
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    • 1999
  • A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.

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Implementation of Ka-band Satellite Broadcasting/LNB with High Dynamic Range (Ka-band 고감도 위성방송용/LNB 최적화 설계)

  • Mok, Gwang-Yun;Lee, Kyung-Bo;Rhee, Young-Chul
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.66-69
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    • 2016
  • In this paper, we suggests a Ka-band LNB considering next-generation UHD satellite TVRO. Since Ka-band has grater attenuation than Ku-band in atmosphere, we designed the low-noise down-converter to improve receiving sensitivity and to extend a dynamic range of receiver. It aims to compensate a quality of ultra high definition transmission signal for rainfall. The low-noise block diagram consists of a three-staged amplifier (LNA), band-pass filter for deleting image (BPF), mixer and IF when considering nonlinear characteristics in the receiver RF front end module. Also, we showed a LNB through optimization processes affecting dynamic range directly in receiver FEM. Asa resuly of experiment, the gain of low-noise down-converter show between 58.5dB and 60.7dB, the noise figure has a high characteristic as 1.38dB. Finally, the phase noise of local oscillator is -63.10dBc at 100MHz offset frequency.

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Design and Implementation of Frequency Down Converter for Satellite Communication (위성 통신용 주파수 하향 변환기의 설계 및 제작)

  • Lee, Seung-Dae;Na, Sang-Yeob
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.2
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    • pp.801-807
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    • 2012
  • In this paper, design and implementation of frequency down converter based on LC filter technic. Single frequency down converter, designed a low-noise amplifier, mixer, IF amplifier, LC filter was configured. And it is composed of DC block capacitors and RF bypass capacitor. LC filter, replace it with the IC reduced the power and realized low cost. The gain of single down converter is about 10dBm and realized by 18MHz bandwidth at 70MHz band.

A Study on the Design of Dual-Band Mixer for WLAN 802.11a/b/g Applications (802.11a/b/g WLAN용 이중대역 혼합기 설계에 관한 연구)

  • Park Wook-Ki;Go Min-Ho;Kang Suk-Youb;Park Hyo-Dal
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.11 s.102
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    • pp.1106-1113
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    • 2005
  • This paper presents a dual-band mixer for multi-standards of IEEE 802.1la/b/g using a single local oscillator, so as to improve the defects of legacy systems. Those systems have duplicate local oscillators and mixers to handle dual band signals, increasing complexity of system and power loss. The proposed circuit shows 11.6 dB, 16.8 dB of conversion loss and 8.77 dBm, 12.5 dBm of IIP3(Input 3rd Intercept Point) for respective bands when the two RF inputs of 2.452 and 5.260 GHz are down-converted to the identical 356 MHz If frequency. The RF-LO isolations are measured 36 dB, 41 dB at each frequencies and over 50 dB of LO-IF isolations are achieved at all cases.

Design of the RF Front-end for L1/L2 Dual-Band GPS Receiver (L1/L2 이중-밴드 GPS 수신기용 RF 전단부 설계)

  • Kim, Hyeon-Deok;Oh, Tae-Soo;Jeon, Jae-Wan;Kim, Seong-Kyun;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.21 no.10
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    • pp.1169-1176
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    • 2010
  • The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.