• Korean Journal of Heritage: History & Science
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• v.52 no.2
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• pp.142-171
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• 2019

The dragon is an imaginary animal that appears in the legends and myths of the Orient and the West. While dragons have mostly been portrayed as aggressive and as bad omens in the West, in the Orient, as they symbolize the emperor or have an auspicious meaning, dragons signify a positive meaning. In addition, as the dragon symbolizes the emperor and its type has been diversified considering it as a divine object that controls water, people have tried to express it as a figure. The records related to dragons in the Goryeo dynasty appeared with diverse topics in 'History of Goryeo' and are generally contents related to founding myths, rituals for rain, and Shinii (神異), etc. The founding myth emphasizes the legality of the Goryeo dynasty through the dragon, and this influenced the formation of the dragon's descendants. In addition, the ability to control water, which is a characteristic of the dragon, was symbolized as an earth dragon related to the rainmaking ritual, i.e., wishing for rain during times of drought. Since the dragon was the symbol of the royal family, the use of the dragon by common people was strictly restricted. Furthermore, the association of a bronze dragon mirror with the royal family is hard to be excluded. The type and quantity of bronze double dragon mirrors discovered to have existed during the Goryeo dynasty is great, and the production and the distribution of bronze mirrors with double dragons seem to have been more active compared to other bronze mirrors, as bronze mirrors with double dragons produced during Goryeo and bronze mirrors originating in China were mixed. Therefore, in this article, the characteristics of diverse bronze mirrors from the 10th century to the 14th century in China were examined. It seems that the master craftsmen who produced bronze mirrors with double dragons during the Goryeo dynasty were influenced by Chinese composition patterns when making the mirrors. Because there were many cases where a bronze mirror's country of origin could not easily be determined, in order to identify the differences between bronze double dragon mirrors produced during the Goryeo dynasty and bronze mirrors produced in China, meticulous analysis was required. Thus, to ascertain that Goryeo mirrors were not imitations of bronze mirrors with double dragons originating in China but produced independently, the mirrors were examined using the bronze double dragon mirror type classification system existing in our country. Bronze mirrors with double dragons are classified into three types: Type I, which has the style of the Yao dynasty, includes the greatest proportion; however, despite there being only a small quantity for comparison, Types II and III were selected for the analysis of the bronze mirrors with double dragons made in Goryeo because they have unique composition patterns. As mentioned above, distinguishing bronze mirrors made during Goryeo from bronze mirrors made in China is challenging because Goryeo bronze mirrors were made under the influence of China. Among them, since the manufacturing place of the bronze mirrors with double dragons found at the nine-story stone pagoda in Woljeongsa Temple in Pyeongchang is questionable and the composition pattern of the bronze mirror is hard to find on bronze mirrors with double dragons made in China, the manufacturing place of those bronze mirrors were examined. These bronze mirrors with double dragons were considered as bronze mirrors with double dragons made during the Goryeo dynasty adopting the Yao dynasty style composition pattern as aspects of the composition pattern belonged to Type I, and the detailed combination of patterns is hard to find in mirrors produced in China.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.55-60
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• 2007

This paper presents a compact double resolution scheme for the optical angle sensor based on 1-dimensional CMOS photodiode pixel array. All the pixels are divided into the even pixel and the odd pixel groups. The winner take all circuit is provided for each group. The proposed interpolation scheme increases the resolution by 2 from the winner addresses and winner values. The interpolation scheme can be implemented without any additional pixels or winner take all circuits and require only a comparator and a XOR gate. The proposed pixel array chip that has 336 photodiode pixels with $5.6{\mu}m$ pitch was fabricated with $0.35{\mu}m$ CMOS process and was assembled with a $50{\mu}m$ slit to form an angle sensor. The measured resolution is $0.1{\circ}$ with the proposed interpolation. The chip consumes 35mW and provides 8k samples per second.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.709-712
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• 2008

본 연구에서는 이중게이트 MOSFET 제작시 가장 중요한 요소인 채널도핑농도가 전송특성에 미치는 영향을 분석하고자 한다. 이를 위하여 분석학적 전송모델을 사용하였으며 분석학적 모델을 유도하기 위하여 포아슨방정식을 이용하였다. 나노구조 이중게이트 MOSFET에서 문턱전압이하의 전류전도에 영향을 미치는 열 방사전류와 터널링전류에 대하여 분석하였으며 본 연구의 모델이 타당하다는 것을 입증하기 위하여 서브문턱스윙값과 채널도핑농도의 관계를 이차원 시뮬레이션 값과 비교하였다. 결과적으로 본 연구에서 제시한 전송특성모델이 이차원 시뮬레이션모델과 매우 잘 일치하였으며 이중게이트 MOSFET의 구조적 파라미터에 따라 전송특성을 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.110-119
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• 2017

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

• Journal of Families and Better Life
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• v.11 no.1
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• pp.119-133
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• 1993

Based on the Double ABCX model of family stress and adaptation this study was to investi-gate the intercorrelations among and the relative magnitutide of variables associated with diffe-rent levels of adaptation to conflict with mothers-in-law reported by daughter-in-law. Frequency of conflict was selected as a stressor(aA) Resource factor(bB) in this study was self-efficacy. Four types of blame(self-behavior self-character other people and impersonal world blame) were selected as perception factors(cC). The adaptation factors(xX) were the level of daughter-in-law's psychological well-being and marital adjustment. Data for this research were questionnaire responses from 151 daughters-in-law who lived in Seoul. The results of correlational analyses indicated that most variables were significantly correlated with each other. In addition results of the path analysis on daughter-in-law's psychological well-being indicated that higher scores on the psychological well-being were significantly associa-ted with(a) greater self-behavior blame for the conflict and (b) less ascription of blame to the impersonal world. Frequency of conflict influenced psychological well-being indirectly th-rough self-behavior blame and impersonal blame both of which were also found to mediate the effect of self-efficacy on the level of psychological well-being. However although all indepen-dent variables were significantly correlated with marital adjustment no variables had direct effects on marital adjustment.

• Journal of Power Electronics
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• v.17 no.1
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• pp.242-252
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• 2017

This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.