• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.664-667
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• 2011

In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.479-479
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• 2011

Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

• Design & Manufacturing
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• v.17 no.4
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• pp.42-51
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• 2023

In this study, we investigated the injection molding technology of thick-walled light guides, which are parts that control the light source of automotive lamps. Through injection molding analysis, the gate position that can minimize product shrinkage and deformation was selected, and a mold reflecting the analysis results was manufactured to evaluate the effect of injection speed and holding pressure on transferability during micro-pattern molding through experiments. When designing an injection mold for products with varying thicknesses, it was found that installing the gate on the side of the thicker part was advantageous for reducing volume shrinkage and deformation. It was found that the effect of shrinkage due to thickness may be greater than the position of the gate on pattern transferability. The pattern transfer error decreased as the injection speed and holding pressure increased, and it was found that increasing the injection speed was relatively effective.

• Journal of Korean Society of Transportation
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• v.26 no.5
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• pp.205-216
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• 2008

As the aged and physically disabled people are expected to increase in the next several years, traffic demand especially for the 'mobility handicapped people' will be stronger. According to this trend, our society needs the improvement of social overhead capital for the aged and the disabled. First of all, Barrier-free of public transport facilities is urgent case. The purpose of this study is to estimate value of the Barrier-free facilities at subway stations by using Contingent Valuation Method(CVM) with Double Bounded Dichotomous Choice Question and to analyze the factor which affects the WTP(Willingness To Pay) of subway users by using Survival Analysis. As a result of this study, 'Elevators' and 'Escalators' are higher than 'Handicapped Gate Machines' and 'Ramps for Wheelchair' in the aspect of the average willingness to pay. Therefore the government is recommended to install the Barrier-free facilities for going up and down such as 'Elevators' and 'Escalators', and then supply others for just using subway, and passing such as 'Handicapped Gate Machines' and 'Ramps for Wheelchair'. Also, the average willingness to pay of 'mobility handicapped people' is higher than that of 'normal people'. It indicates that 'mobility handicapped people' value each Barrier-free facility high compared to 'normal people'.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.869-875
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• 2017

Using TCAD simulation, performances of tunnel field-effect transistors (TFETs) was investigated. Drain current-gate voltage types of TFET structure such as single-gate TFET (SG-TFET), double-gate TFET (DG-TFET), L-shaped TFET (L-TFET), and Pocket-TFET (P-TFET) are simulated, and then as dielectric constant of gate oxide and channel length are varied their subthreshold swing (SS) and on-current ($I_{on}$) are compared. On-currents and subthreshold swings of the L-TFET and P-TFET structures with high electric constant and line tunneling were 10 times and 20 mV/dec more than those of the SG-TFET and DG-TFET using point tunneling, respectively. Especially, it is shown that hump effect which dominant current element changes from point tunneling to line tunneling, is disappeared in P-TFET with high-k gate oxide such as $HfO_2$. The analysis of 4 types of TFET structure provides guidelines for the design of new types of TFET structure which concentrate on line tunneling by minimizing point tunneling.

• The Sea:JOURNAL OF THE KOREAN SOCIETY OF OCEANOGRAPHY
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• v.6 no.3
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• pp.115-125
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• 2001

To examine the movement of the freshwater discharged artificially into the estuary during ebbing period in the Keum River dike we observed surface salinity variations in three stations along the estuary channel in May 1998 and July 1997 and surface temperature and salinity along the ferry-route between Kunsan and Changhang during eighteen days in July 1999. Based upon the typical features of observed salinity variation, we analyzed the excursion and decay processes of the discharged water. When freshwater is discharged, the low-salinity water forms strong salinity front over the entire estuary width, which basically moves forth and back by tidal modulation along the channel, producing the sudden change of surface salinity with the front passage. Salinity distribution along the channel, which is deduced from time variation of mean salinity over the estuary width, after one tidal period from gate operation suggests that diluted low-salinity water is trapped to the front and surface salinity increases gradually toward the upstream region. This frontal distribution of salinity is interpreted to be produced by the sudden gate operation supplying and stopping of freshwater within about two hours. Daily repeat of freshwater discharge produces separation (double front) or merge between decaying and new-generated fronts depending on dike-gate opening time, and the front decays with salinity increasing if the freshwater supply is stopped more than two days. In addition, the observed fluctuations and deviations in surface salinity variation is explained in terms of the differences of fronts intensity, their transition time and temporal salinity front running along the channel, which can be generated due to artificial gate-operation for the discharging time and water volume in the estuary dike.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.72-81
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• 2011

In this paper, we proposed and designed a novel floating point converter which supports single and double precisions of IEEE754 standard. The proposed convertor supports conversions between floating point number single/double precision and signed fixed point number(32bits/64bits) as well as conversions between signed integer(32bits/64bits) and floating point number single/double precision and conversions between floating point number single and double precisions. We defined a new internal format to convert various input types into one type so that overflow checking could be conducted easily according to range of output types. The internal format is similar to the extended format of floating point double precision defined in IEEE754 2008 standard. This standard specifies that minimum exponent bit-width of the extended format of floating point double precision is 15bits, but 11bits are enough to implement the proposed converting unit. Also, we optimized rounding stage of the convertor unit so that we could make it possible to operate rounding and represent correct negative numbers using an incrementer instead an adder. We designed single cycle data path and 5 cycles data path. After describing the HDL model for two data paths of the convertor, we synthesized them with TSMC 180nm technology library using Synopsys design compiler. Cell area of synthesis result occupies 12,886 gates(2 input NAND gate), and maximum operating frequency is 411MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.367-373
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• 2001

A programmable A/D converter is designed with 8 N and P channel MOSFETs, respectively. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a 1.2 ${\mu}{\textrm}{m}$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10m Volt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, 37㎽ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Asian Pacific Journal of Cancer Prevention
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• v.13 no.12
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• pp.6087-6091
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• 2012

Context: Patients diagnosed with a cancer have a life time risk of developing another de novo malignancy depending on various inherited, environmental and iatrogenic risk factors. Of late the detection of new primary has increased mainly due to refinement in both diagnostic and treatment modalities. Cancer victims are surviving longer and thus are more likely to develop a new metachronous malignancy. Aims: To report our observed trend of increase in prevalence of both synchronous and metachronous second malignant neoplasms among cancer victims and to review the relevant literature. Settings and Design: A hospital based retrospective collection of prospective data of patients diagnosed with second denovo malignancy. Materials and Method: The study was conducted over a 5 year period from July 2008 to June 2012. All patients diagnosed with a histologically proven second malignancy as per Warren Gate's criteria were included. Various details regarding sex, age at presentation, synchronous or metachronous, treatment and outcome were recorded. Conclusions: The occurrence of multiple primary malignancies is not rare. Awareness of the possibility alerts the clinician in evaluation of patients with a known malignancy presenting with unusual sites of metastasis. Individualizing the treatment according to the stages of the primaries will result in durable cancer control particularly in synchronous double malignancy.