• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• 전자공학회논문지C
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• 제34C권6호
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• 전력전자학회논문지
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• 제21권5호
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• pp.381-387
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• 2016

Many efforts have focused on the improvement of power density and efficiency by downsizing the motor and inverter. Recently, Toyota, Honda, and GM realized that the compact-sized motor uses the hairpin structure with increased space factor. Reducing the maximum torque from high-speed technique also makes it possible to design the high-power density model. Toyota and Honda used the newly developed power semiconductor IGBT to decrease conduction loss for high-efficiency inverter. In particular, Toyota used the boost converter to increase the DC link voltage for high efficiency in low-torque high-speed region. Toyota and GM also used the double-sided cooling structure for miniaturization of inverter for high-power density.

• Journal of Power Electronics
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• 제11권5호
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• pp.655-661
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• 2011

This paper presents two topologies for single-stage single-phase double-buck type PFC converters, designed to operate at high power factor, near sinusoidal input currents and adjustable output voltage. Unlike the known buck type PFC topologies, in which the output voltage is always lower than the maximum input voltage, the proposed converters can operate at output voltages higher than the ac input peak voltage. A reduced number of switches on the main path of the current are another characteristic of the two proposed topologies. To shape the input line currents, a fast and robust controller based on a sliding mode approach is proposed. This active non-linear control strategy, applied to these converters allows high quality input currents. A Proportional Integral (PI) controller is adopted to regulate the output voltage of the converters. This external voltage controller modulates the amplitude of the sinusoidal input current references. The performances of the presented rectifiers are verified with experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2015년도 전력전자학술대회 논문집
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• pp.321-322
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• 2015

The aim of this paper is to propose a design method for the double-sided LCC compensation circuit for 6.6kW electric vehicle (EVs) wireless charger. The analysis and comparison with several compensation topologies such as SS, SP, PS, PP and the hybrid LCC compensation is presented. It has been found that the hybrid LCC compensation has superior performance in comparison with other topologies. The design procedure for the EV charger is presented and the PSIM simulation results are provided.

• Journal of Power Electronics
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• 제17권4호
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• pp.1004-1013
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• 2017

This paper presents an interleaving scheme for parallel-connected power systems to reduce the DC-link current ripple. A paralleled generator system generates current ripple by the Pulse Width Modulation (PWM) of each generator side converter. The current ripple in the DC-link degrades the efficiency of the whole generator system and decreases the lifetime of the DC-link capacitors. To mitigate these issues, the expression of the DC-link current is derived by a double-integral Fourier analysis while considering the modulation schemes. Optimized interleaving angles for the parallel generator system are obtained based on an analysis to minimize the dominant current harmonics component. Finally, the proposed interleaving scheme reduces the RMS value of the DC-link current ripple. Simulation and experimental results verify the effectiveness of the proposed interleaving scheme.

• 대한전자공학회논문지SD
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• 제38권5호
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• pp.55-55
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• 2001

개의 N과 P채널 EEPROM을 이용하여 A/D 변환기를 설계하였다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 1.2㎛ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10㎷ 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/D 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 37㎼의 전력을 소모하고 동작주파수는 333㎒ 정도인 것으로 관찰되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 하계학술대회 논문집
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• pp.31-33
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• 1991

A passive power converter operating on the principle of parametric excitation, called Parametric transformer, is analyzed. The energy transfer from the input to the output is achieved through the double frequency variation of magnetic path reluctance to the input frequency without mutual flux coupling between two windings. Thus, output becomes available which is essentially independant of waveform of excitation. The mathmatical model of the device is developed and its solution is obtained. The outstanding characteristics of the device is explained from the analysis.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.128.1-128
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• 2001

A propulsion system apparatus is needed for a railroad vehicle to test and estimate propulsion performance. The electrical inertia simulator to facilitate the development and testing of propulsion systems, is presented in this paper. It is based on a vector-controlled Induction motor drive supplied from the AC mains through a double PWM converter that provides desirable features such as hi-directional power folw, nearly unity power factor and low harmonic factor at the Ac mains. A theoretical analysis is first presented, followed by a detailed simulation study to assess the overall system performance under dynamic conditions.