• Journal of Power Electronics
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• v.12 no.2
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• pp.249-257
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• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Transactions of the Korean Society of Automotive Engineers
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• v.6 no.4
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• pp.108-120
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• 1998

A theoretical study of three-dimensional unsteady compressible non-reacting flow inside double flow of monolith catalytic converter system attached to 6-cylinder engine was performed for the achievement of performance improvement, reduction of light-off time, and longer service life by improving the flow distribution of pulsating exhaust gases. The differences between unsteady and steady-state flow were evaluated through the numerical computations. To obtains the boundary conditions to a numerical analysis, one dimensional non-steady gas dynamic calculation was also performed by using the method of characteristics in intake and exhaust system. Studies indicate that unsteady representation is necessary because pulsation of gas velocity may affect gas flow uniformity within the monolith. The simulation results also show that the level of flow maldistribution in the monolith heavily depends on curvature and angles of separation streamline of mixing pipe that homogenizes the exhaust gas from individual cylinders. It is also found that on dual flow converter systems, there is severe interactions of each pulsating exhaust gas flow and the length of mixing pipe and junction geometry influence greatly on the degree of flow distribution.

• Journal of Power Electronics
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• v.13 no.3
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• pp.419-428
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• 2013

The modular multilevel cascade converter (MMCC) is a new family of multilevel power converters with modular realization and a cascaded pattern for submodules. The MMCC family can be classified by basic configurations and submodule types. One member of this family, the Hexverter, is configured as Double-Delta Full-Bridge (DDFB). It is a novel multilevel AC/AC converter with direct power conversion and comparatively fewer required components. It is appropriate for connecting two three-phase systems with different frequencies and driving an AC motor directly from a utility grid. This paper presents the dq model of a Hexverter with both of its AC systems by state-space representation, which then simplifies the continuous time-varying model into a periodic discrete time-invariant one. Then a generalized multivariable optimal control strategy for regulating the Hexverter's independent currents is developed. The resulting control structure can be adapted to other MMCCs and is flexible enough to include other control criterion while guaranteeing the original controller performance. The modeling method and control design are verified by simulation results.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.278-284
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• 1998

This paper describes a l0b CMOS A/D converter (ADC) for HDTV applications. The proposed ADC adopts a typical multi-step pipelined architecture. The proposed circuit design techniques are as fo1lows: A selective channel-length adjustment technique for a bias circuit minimizes the mismatch of the bias current due to the short channel effect by supply voltage variations. A power reduction technique for a high-speed two-stage operational amplifier decreases the power consumption of amplifiers with wide bandwidths by turning on and off bias currents in the suggested sequence. A typical capacitor scaling technique optimizes the chip area and power dissipation of the ADC. The proposed ADC is designed and fabricated in s 0.8 um double-poly double-metal n-well CMOS technology. The measured differential and integral nonlinearities of the prototype ADC show less than ${\pm}0.6LSB\;and\;{\pm}2.0LSB$, respectively. The typical ADC power consumption is 119 mW at 3 V with a 40 MHz sampling rate, and 320 mW at 5 V with a 50 MHz sampling rate.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.57-66
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• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.2 no.2 s.3
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• pp.97-101
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• 2003

A MMIC (monolithic microwave integrated circuit) mixer chip using the Schottky diode of an InGahs/CaAs p-HEMT process has been developed for the receiver down converter of Ku-band. A different approach to the MMIC mixer structure is applied for reducing the chip size by the exchange of ports between If and LO. This MMIC covers with RF (14.0 - 14.5 GHz) and If (12.252 - 12.752 GHz). According to the on-wafer measurement, the miniature (3.3X3.0 m) MMIC mixer demonstrates conversion loss below 9.8 dB, RF-to-IF isolation above 23 dB, LO-to-IF isolation above 38 dB, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.697-701
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• 1996

King Sejong's Striking water-clock which brought in use on the first of July in 1434 was mainly composed of timekeeping and time announcing parts signalling twelve double-hours, and five night-watches and night-watch-divisions automatically by means of ball-operating jackworks. The clock was arranged with dual timekeeping system, the one for a full day(twelve double-hours) and the other for five night-watches achieving twelve double-hours and one-hundred interval horary systems. The vessels were arrayed in inflow-type water-clock, a large reservoir on the highest story, a constant-level tank for supplying water to the measuring vessel evenly in the middle, and the lowest tank to receive water from the above constant-level tank. An indicator-rod on the float was raised upwards depending on the water-level increase to show timing scales and also to release small bronze balls from the ball-rack mechanisms implanted on the measuring vessel to signal timing intervals.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1366-1379
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• 2019

High-gain DC/DC converters have become one of the key technologies for the grid-connected operation of new energy power generation, and its research provides a significant impetus for the rapid development of new energy power generation. Inspired by the transformer effect and the ripple-suppressed ability of a coupled inductor, a double-coupled inductor high gain DC/DC converter with a ripple absorption circuit is proposed in this paper. By integrating the diode-capacitor voltage multiplying unit into the quadratic Boost converter and assembling the independent inductor into the magnetic core of structure coupled inductors, the adjustable range of the voltage gain can be effectively extended and the limit on duty ratio can be avoided. In addition, the volume of the magnetic element can be reduced. Very small ripples of input current can be obtained by the ripple absorption circuit, which is composed of an auxiliary inductor and a capacitor. The leakage inductance loss can be recovered to the load in a switching period, and the switching-off voltage spikes caused by leakage inductance can be suppressed by absorption in the diode-capacitor voltage multiplying unit. On the basis of the theoretical analysis, the feasibility of the proposed converter is verified by test results obtained by simulations and an experimental prototype.