• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.323-329
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• 2017

This reports the electrical behavior, bonding structure and Schottky contact of gallium-zinc-oxide (GZO) thin film annealed at $100{\sim}400^{\circ}C$. The mobility of GZO with high density of PL spectra and crystal structure was also increased because of the structural matching between GZO and Si substrate of a crystal structure. However, the GZO annealed at $200^{\circ}C$ with an amorphous structure had the highest mobility as a result of a band to band tunneling effect. The mobility of GZO treated at low annealing temperatures under $200^{\circ}C$ increased at the GZO with an amorphous structure, but that at high temperatures over $200^{\circ}C$ also increased when it was the GZO of a crystal structure. The mobility of GZO with a Schottky barrier (SB) was mostly increased because of the effect of surface currents as well as the additional internal potential difference.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.12
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• pp.2166-2172
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• 2007

In this study a low-signal equivalent circuit based on the Double Schottky Barrier model is proposed for ZnO-based varistor. Since pin-lead inductance and stray capacitance are considered in pin-lead type ZnO varistor these inductance and capacitance could be removed from the experimental dielectric data of the varistor. According to the equivalent circuit simulation results the higher the varistor-voltage of varistor sample the capacitance of dielectric layer is larger, and the capacitances of semiconducting layer and depletion layer are smaller, while the parallel resistances of semiconducting layer and depletion layer are more larger values. Spectra of the dielectric loss factor $tan{\delta}$ show 2 peaks in low frequency and high frequency regions respectively. The low-frequency peak is due to the relaxation by deep donors and the high-frequency peak is due to the relaxation by shallow donors. Above results are well consistent with the theoretical mechanism of ZnO varistor.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.11-16
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• 2016

Silicon carbide (SiC) has received significant attention over the past decade because of its high-voltage, high-frequency and high-thermal reliability in devices compared to silicon. Especially, a SiC Schottky barrier diode (SBD) is most often used in low-voltage switching and low on-resistance power applications. However, electric field crowding at the contact edge of SBDs induces early breakdown and limits their performance. To overcome this problem, several edge termination techniques have been proposed. This paper proposes an improvement in the breakdown voltage using a double-field-plate structure in SiC SBDs, and we design, simulate, fabricate, and characterize the proposed structure. The measurement results of the proposed structure, demonstrate that the breakdown voltage can be improved by 38% while maintaining its forward characteristics without any change in the size of the anode contact junction region.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.04a
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• pp.206-210
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• 1986

Double Ion Implantation methods are used to improve the stiffness os carrier profiles, and then the analytical solutions to Poisson`s equation are derived with summation of each carrier profile. Numerical analyses are done using profer boudary conditions and the results show that the improvement of voltage-dependent-capacitance ratio (C(!)/C(25)) is obtained up to B.6. The third ion implantation is for the enhancement of the Schottky barrier height.

• Electrical & Electronic Materials
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• v.9 no.7
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• pp.708-718
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• 1996

The microstructure and electrical properties of the nonlinear ZnO varistor with A1$_{2}$ $O_{3}$ additions is investigated. The variation of nonlinear behavior with A1$_{2}$ $O_{3}$ additions is indicated from J-E and C-V measurement to be a result of the change of the interface defects density $N_{t}$ at the grain boundaries and the donor concentration $N_{d}$ in the ZnO grains. The optimum composition which has the nonlinear coefficients of -57 was observed in the sample with 0.005wt% A1$_{2}$ $O_{3}$ additions. The conduction mechanism at the pre-breakdown region is consistent with a Schottky thermal emission process obeying a relation given by $J^{\var}$exp[-(.psi.-.betha. $E^{1}$2/)kT] and the conduction process at the breakdown region follows a Fowler-Nordheim tunneling mechanism of the form $J^{\var}$exp(-.gamma./E).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• Journal of the Korean Ceramic Society
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• v.40 no.10
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• pp.921-924
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• 2003

A current-voltage relation for Positive Temperature Coefficient of Resistance (PTCR) ceramic was derived and compared with the experimental data. The new current-voltage relation was developed based on Heywangs double Schottky barrier model and a bias distribution across the grain boundary. The voltage limitation V < 4${\Phi}$$\sub$b/ suggested by Heywang is no longer necessary in the new expression for the voltage dependence of the resistance. The pulsed voltages were applied to the PTCR ceramic specimen in order to avoid possible temperature variation during the measurement.

• Journal of Sensor Science and Technology
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• v.28 no.4
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• pp.231-235
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• 2019

We investigated the facile and effective strategy for sensitive and selective $C_2H_5OH$ sensors based on the In-decorated NiO nanoigloos. The In-decorated NiO nanoigloos is fabricated by RF sputtering using 750 nm-diameter polystyrene beads using a soft-template. The morphological evolution based on the Van der Drift model was generated through a heterojunction between In metal and NiO, resulting in a pyramidal rough surface. Upon decorating the In on the NiO surface, high sensitivity and selectivity to $C_2H_5OH$ were observed, and gas sensing mechanism was demonstrated by a high surface-to-volume and double Schottky barrier. We are confident that the method presented in this study will have a significant impact on the fabrication of effective nanostructures and their application for the gas sensors.