• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.17-25
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• 2004

In this paper, we propose a new small swing domino logic for low-power consumption. To reduce the power consumption, both the precharge node and the output node swing the range from 0 to $V_{REF}$- $V_{THN}$, where $V_{REF}$=VDD-n $V_{THN}$ (n=1, 2, and 3). This can be done by adding the inverter structure on domino logic that allows a full swing or a small swing on its input terminal without leakage current. Compared to previous works, the proposed structure can save the power consumption of more than 30% for n=0, 1, 2, and 3 in the equation of $V_{REF}$=VDD-n $V_{THN}$. A multiplier applying the proposed domino logic has been designed and fabricated using a 0.35-${\mu}{\textrm}{m}$ n-well CMOS process under 3.3-V supply voltage. Compared with other previous works, it shows a 30% power reduction and a better feature in power-delay product.lay product.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.4
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• pp.787-794
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• 1999

This paper presents an ENMODL(enhances NORA MODL) circuit and implements a high-speed 32 bit CLA(carry lookahead adder) with the new dynamic logics. The proposed logic can reduce the area and the Propagation delay of carry because output inverters and a clocking PMOS of second stage can be omitted in two-stage MODL(multiple output domino logic) circuits. The 32-bit CLA is implemented with 0.8um double metal CMOS Process and the carry propagation delay of the adder is about 3.9 nS. The ENMODL circuits can improve the performance in the high-speed computing circuits depending on the degree of recurrence.