• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.821-824
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• 1999

In distributed arithmetic-based architecture for an inner product between two length-N vectors, the size of the ROM increases exponentially with N. Moreover, the ROMs are generally the bottleneck of speed, especially when their sire is large. In this paper, a ROM size reduction technique for DA (Distributed Arithmetic) is proposed. The proposed method is based on modified OBC (Offset Binary Coding) and control circuit reduction technique. By simulations, it is shown that the use of the proposed technique can result in reduction in the number of gates up to 50%.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권9호
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• 한국통신학회논문지
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• 제25권3B호
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• pp.584-591
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• 2000

본 논문에서는 벡터의 내적에 사용되는 Distributed Arithmetic의 ROM 면적을 줄일 수 있는 방법을 제시한다. 제안된 방법을 이용하여 만든 ROM table은 그 크기가 기존 방법에 비해 반으로 감소되며 새로 생성된 ROM table에 같은 방법을 반복 적용함으로써 그 크기를 계속 1/2씩 감소시킬 수 있다. 반면에 ROM table을 반으로 줄일 때마다 논리회로의 첨가로 인한 하드웨어의 증가와 critical path의 증가가 발생하는데, 이들 오버헤드를 최소화할 수 있는 방법과 전체적인 면적 감소 효과를 극대화 할 수 있는 방법을 함께 제시한다. 제시한 방법을 적용함으로써 약 50%까지의 하드웨어를 감소시킬 수 있음을 예를 통하여 보인다.

• 대한전자공학회논문지SP
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• 제43권1호
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• pp.101-108
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• 2006

이 논문에서는 64-Point FFT Radix-4 알고리즘을 DA(Distributed Arithmetic)연산을 이용하여 효율적으로 나비연산 구조를 설계할 수 있음을 보였다. 기존의 convolution 연산에 사용되어 왔던 DA연산이 FFT 나비연산의 트위들 계산에도 효과적으로 사용될 수 있음을 보였다. 제안된 DA 나비연산 구조를 Verilog HDL 코딩으로 구현한 결과, 기존의 승산기를 사용한 나비연산 구조와 비교하여 $61.02\%$의 cell area 감소 효과를 보였다. 또한 제안된 나비연산 구조를 파이프라인 구조에 적용하여 지연변환기와 함께 사용한 전체 64-point Radix-4 FFT 구조의 Verilog-HDL 코딩을 기존의 승산기를 사용한 구조의 코딩과 비교한 결과, $46.1\%$의 cell area 감소효과를 볼 수 있었다. 따라서 제안된 FFT 구조는 DMB용 OFDM 모뎀과 같은 큰 크기의 FFT에 효율적으로 사용될 수 있는 구조가 될 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.116-119
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• 2000

The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.

• 전자공학회논문지A
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• 제31A권6호
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• pp.188-198
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• 1994

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.678-681
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• 2002

In this paper, we propose a block LMS algorithm using distributed arithmetic (BDA) and a multi-memory block structured BDA (MBDA). Moreover, we propose an effective VLSI architecture of adaptive digital filter using MBDA, and evaluate the sampling rate and output latency.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 춘계학술발표회 논문집
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• pp.177-180
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• 1986

A high performance Butterfly Arithmetic Unit for FFT processor using two adders is proposed in this papers, which is Based on the distributed and merged arithmetic. Due to simple and easy architecture to implement, this proposed processor is well suited to systolic FFT processor. Simulation was performance using YSLOG (Yonsei logic simulator) on IBM AT computer, to verify logic. By using 3um double Metal CMOS technology,Butterfly arithmetic have been achieved in 1.2 usec.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.636-639
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• 2004

In present, there are many methods such as DCT, Wavelet Transform, or Quantization -to the image compression field, but the basic image compression method have based on DCT. The representative thing of the efficient techniques for information compression is DCT method. It is more superior than other information conversion method. It is widely applied in digital signal processing field and MPEG and JPEG which are selected as basis algorithm for an image compression by the international standardization group. It is general that DCT is consisted of using multiplier with main arithmetic blocks having many arithmetic amounts. But, the use of multiplier requires many areas when hardware is embodied, and there is fault that the processing speed is low. In this paper, we designed the hardware module that could run high-speed operation using row-column separation calculation method and Chen algorithm by distributed arithmetic method using ROM table instead of multiplier for design DCT module of high speed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.