• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.277-279
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• 2008

In this paper, a novel active boost converter for SR drive is proposed. An active capacitor circuit is added in the front-end. Based on this active capacitor network, when boost switch turns off, this network seems as passive capacitor network. And the voltage of boost capacitor can keep balance with dc-link voltage automatically. In the capacitor network, discharging voltage is general dc-link voltage in parallel-connected capacitors; charging voltage is double dc-link voltage in series-connected capacitors. When boost switch turns on, two capacitors are connected in series, and discharging voltage is up to double dc-link voltage. So the fast excitation current can be obtained from this mode. Profit from fast excitation and fast demagnetization mode, the performance and output power can be improved. Some computer simulations are done to verify the performance of proposed converter.

• 한국산학기술학회논문지
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• 제15권8호
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• pp.5213-5218
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• 2014

유기메모리 제작을 위해 플라즈마 중합법에 의해 절연박막, 터널링 박막을 제작하였고, Au 메모리박막을 이용하여 플로팅게이트형 유기메모리를 제작하였다. 플로팅 게이트형 유기메모리의 메모리층의 전하충전 및 방전에 따른 유기메모리 동작특성을 생각해 보았고, 이를 증명하고자 게이트전압에 따른 히스테리전압 및 메모리전압을 측정하였다. 그 결과 게이트 전압의 인가에 따른 메모리층의 동작 이론을 증명하고자 게이트전압이 증가함에 따른 소스-드레인 전류의 히스테리시스 현상이 심해지는 것을 확인하였고, -60~60[V]전압 인가시 26[V]의 큰 히스테리시스 전압값을 보였다. 또한 게이트 전극에 쓰기전압인가에 따른 현상을 본 결과, 60[V]의 쓰기 전압을 인가하였을 시 13[V]의 memory 전압을 나타내었고, 80[V]의 쓰기전압을 인가하였을 시 18[V]로 memory 전압이 약 40[%] 향상된 수치를 보였다. 이로부터 메모리층의 전하 충전 및 방전에 따른 메모리 동작특성 이론을 실험적으로 검증하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1869-1871
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• 1998

In this paper, we designed and fabricated a fast switching system for high power pulse. This system consists of a voltage conversion circuit, high voltage charging circuit, trigger circuit, and discharging circuit. Especially discharging line is designed by strip-line for low inductance and resistance. The experimental result is that current slew rate of the system is 6.67kA/86ns and this result is fully qualified for initiating EBW or EFI

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.600-603
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• 2001

The method of supplying a single voltage source to a drive has a weak point that we can not determine whether discharging cells of a upper panel in a PDP(Plasma display panel) operate properly or not in the step of testing a durable voltage. From this paper, we can make more reliable products by the design-method of a power-module, for testing a durable voltage, that can determine if discharging cells in a upper pannel in a PDP have something wrong in variously supplied voltage sources.

• 조명전기설비학회논문지
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• 제28권4호
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• pp.56-61
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• 2014

In this paper, a control method using Sinusoidal Filter Controller of Silent Discharging Ozonizer is proposed and also the control methode performed robust control against variation of capacitance, command voltage and frequency. As the control system for this methode, Sinusoidal Filter Algorism can be simplified configuration of the power supply by using a low-pass filter. Through simulations and experiment results, the proposed control methode compensates for the high voltage waveform to the ozonizer.

• 전력전자학회논문지
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• 제23권3호
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• pp.190-198
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• 2018

This paper proposes a nonisolated, bidirectional, soft-switching DC - DC converter with PWM plus phase shift (PPS) control. The proposed converter has an input-parallel/output-series configuration and can achieve the interleaving effect and high voltage gains, resulting in decreased voltage ratings in all related devices. The proposed converter can operate under zero-voltage switching (ZVS) conditions for all switches in continuous conduction mode. The power flow of the proposed converter can be controlled by changing the phase shift angle, and the duty is controlled to balance the voltage of four high voltage side capacitors. The PPS control device of the proposed converter is simple in structure and presents symmetrical switching patterns under a bidirectional power flow. The PPS control also ensures ZVS during charging and discharging at all loads and equalizes the voltage ratings of the output capacitors and switches. To verify the validity of the proposed converter, an experimental investigation of a 2 kW prototype is performed in both charging and discharging modes under different load conditions and a bidirectional power flow.

• ETRI Journal
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• 제39권3호
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.361-362
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• 2016

Presented in this paper is the design of a high voltage switch module made up of MOSFETs, pulse transformers and their gate driver circuits compactly fitted onto a single PCB module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier switch synchronization is also described in this paper. The stored energy in the capacitor bank of a 15kV, 4.5kJ/s peak power capacitor charger was discharged using the developed high voltage switch, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.428-431
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• 2003

In this paper, the stress induced leakage currents of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between $113.4{\AA}$ and $814{\AA}$, which have the gate area 10-3cm2. The stress induced leakage currents will affect data retention and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.